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High-Speed Configurable VLSI Architecture of a General Purpose Lifting-Based Discrete Wavelet Processor

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Part of the book series: Communications in Computer and Information Science ((CCIS,volume 48))

Abstract

The richness of wavelet transform has been known in many fields. There exist different classes of wavelet filters that can be used depending on the application. In this chapter, we propose a general purpose lifting-based wavelet processor that can perform various forward and inverse DWTs. Our architecture is based on M processing elements (PEs) that can perform either prediction or update on a continuous data stream in every clock cycle. We also consider the normalization step that takes place at the end of the forward DWT or at the beginning of the inverse DWT. To cope with different wavelet filters and different applications, we feature a multi-context configuration to select among various DWTs and an arbitrary memory size to compute the transform. For the 16-bit implementation, the estimated area of the proposed wavelet processor with 8 PEs and 2x512 words memory in a 0.18-μm technology is 2.3 mm square and the estimated frequency is 347 MHz.

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Guntoro, A., Keil, HP., Glesner, M. (2009). High-Speed Configurable VLSI Architecture of a General Purpose Lifting-Based Discrete Wavelet Processor. In: Filipe, J., Obaidat, M.S. (eds) e-Business and Telecommunications. ICETE 2008. Communications in Computer and Information Science, vol 48. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-05197-5_23

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  • DOI: https://doi.org/10.1007/978-3-642-05197-5_23

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-05196-8

  • Online ISBN: 978-3-642-05197-5

  • eBook Packages: Computer ScienceComputer Science (R0)

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