Abstract
In this paper we address the possibility to improve the reliability of small to middle-size circuits without employing redundancy. Circuits’ reliability is improved by reducing the logic depth of critical paths since the probability of failure of each output of the circuit depends no the logic depth of critical paths. Circuits of the same size were considered, as well as different synthesized versions of the same circuit and the estimation of the probability of failure is given with respect to the logic depth.
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© 2009 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering
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Stanisavljevic, M., Schmid, A., Leblebici, Y. (2009). Optimization of Nanoelectronic Systems Reliability by Reducing Logic Depth. In: Schmid, A., Goel, S., Wang, W., Beiu, V., Carrara, S. (eds) Nano-Net. NanoNet 2009. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 20. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04850-0_11
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DOI: https://doi.org/10.1007/978-3-642-04850-0_11
Publisher Name: Springer, Berlin, Heidelberg
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