FSM Synthesis with Elementary Chains

Abstract

The chapter is devoted to original methods oriented on optimization of Moore FSM interpreting graph-schemes of algorithms with long sequences of operator vertices having only one input. These sequences are named elementary operational linear chains (EOLC). These FSM models include the counter keeping, either microinstruction addresses or code of EOLC component. In the beginning the Moore FSM models with code sharing are analysed, where the register keeps EOLC codes. The methods of EOLC encoding and transformation are discussed; these methods permit to decrease the number of macrocells in the block generating input memory functions. The second part of the chapter is devoted to reduction of the number of embedded memory blocks in the FSM block generating microoperations. These methods are based on transformation of microinstruction address represented as concatenation of EOLC code and code of its component into either linear microinstruction address or code of collection of microoperations. The last part of the chapter discusses synthesis methods for multilevel FSM models with EOLC.