Abstract
The chapter is devoted to design methods based on transformation of an interpreted graph-scheme of algorithm. The methods of decrease for the number of logical conditions per FSM state are discussed. In extreme case, all FSM transitions depend on single logical condition; it allows use of embedded memory blocks for implementation of FSM input memory functions. In this case all FSM blocks are implemented using standard library cells (not just macrocells of a particular FPLD chip). The second part of the chapter is devoted to hardware optimization for block of microoperations, based on verticalization of an interpreted GSA. It permits to decrease the number of decoders (up to 1) and bit capacity of microinstructionword, but this optimization is connected with increase for the number of cycles required for a control algorithm interpretation. At last, the models based on joint application of these methods are discussed.
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Barkalov, A., Titarenko, L. (2009). FSM Synthesis with Transformation of GSA. In: Logic Synthesis for FSM-Based Control Units. Lecture Notes in Electrical Engineering, vol 53. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04309-3_6
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DOI: https://doi.org/10.1007/978-3-642-04309-3_6
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-04308-6
Online ISBN: 978-3-642-04309-3
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