Optimization for Logic Circuit of Mealy FSM

Abstract

The chapter is devoted to the hardware amount reduction in the logic circuit of Mealy FSM. The methods of logical condition replacement are analyzed, as well as different methods of encoding of collections of microoperations (maximal encoding and encoding of the classes of compatible microoperations).Next, the methods of structure table rows encoding are discussed. Each of these methods produces double-level circuit of Mealy FSM. The main part of the chapter is devoted to joint application of these methods, the main advantage of whose is possibility of standard library cells use for implementation of logic circuits for some blocks of an FSM model. For example, the logical condition replacement allows application of multiplexers, whereas the encoding of collections of microoperations permits to use embedded memory blocks. Standard decoders can be used in case of encoding of the classes of compatible microoperations. It increases FSM logic circuit regularity and leads to simplification of its design process.