A Buffer Space Optimal Solution for Re-establishing the Packet Order in a MPSoC Network Processor

  • Daniela Genius
  • Alix Munier Kordon
  • Khouloud Zine el Abidine
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5704)


We consider a multi-processor system-on-chip destined for streaming applications. An application is composed of one input and one output queue and in-between, several levels of identical tasks. Data arriving at the input are treated in parallel in an arbitrary order, but have to leave the system in the order of arrival. This scenario is particularly important in the context of telecommunication applications, where the duration of treatment depends on the packets’ contents. We present an algorithm which re-establishes the packet order: packets are dropped if their earliness or lateness exceeds a limit previously fixed by experimentation; otherwise, they are stored in a buffer on the output side. Write operations to this buffer are random access, whereas read operations are in FIFO order. Our algorithm guarantees that no data is removed from the queue before it has been read. For a given throughput, we guarantee a minimum buffer size. We implemented our algorithm within the output coprocessor in the form of communicating finite state machines and validated it on a multi-processor telecommunication platform.


Transmission Control Protocol Output Side Streaming Application Throughput Requirement FIFO Queue 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Comer, D.: Network System Design using Network Processors. Prentice Hall, Englewood Cliffs (2003)Google Scholar
  2. 2.
    Postel, J.B., Garlick, L.L., Rom, R.: Transmission Control Protocol Specification. Technical report, Stanford Research Institution, Menlo Park (1976)Google Scholar
  3. 3.
    Bennett, J.C.R., Partridge, C., Shectman, N.: Packet reordering is not pathological network behavior. IEEE ACM Transactions on Networking 7, 789–798 (1999)CrossRefGoogle Scholar
  4. 4.
    Bellardo, J., Savage, S.: Measuring packet reordering. In: ACM SIGCOMM Internet Measurement Workshop, pp. 97–105. ACM Press, New York (2002)CrossRefGoogle Scholar
  5. 5.
    Augé, I., Pétrot, F., Donnet, F., Gomez, P.: Platform-based design from parallel C specifications. CAD of Integrated Circuits and Systems 24, 1811–1826 (2005)CrossRefGoogle Scholar
  6. 6.
    Berrayana, S., Faure, E., Genius, D., Pétrot, F.: Modular on-chip multiprocessor for routing applications. In: Danelutto, M., Vanneschi, M., Laforenza, D. (eds.) Euro-Par 2004. LNCS, vol. 3149, pp. 846–855. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  7. 7.
    Kahn, G.: The semantics of a simple language for parallel programming. In: Rosenfeld, J.L. (ed.) Information Processing 1974: Proceedings of the IFIP Congress, pp. 471–475. North-Holland, New York (1974)Google Scholar
  8. 8.
    Faure, E., Greiner, A., Genius, D.: A generic hardware/software communication mechanism for Multi-Processor System on Chip, targeting telecommunication applications. In: Proceedings of the ReCoSoC workshop, Montpellier, France (2006)Google Scholar
  9. 9.
    Genius, D., Faure, E., Pouillon, N.: Deploying a telecommunication application on a multiprocessor system-on-chip. In: Workshop on Design and Architectures for Signal and Image Processing, Grenoble, France (2007)Google Scholar
  10. 10.
    Allen, J.R., et al.: IBM PowerNP network processor: Hardware, software, and applications. IBM Journal of Research and Development 47, 177–193 (2003)CrossRefGoogle Scholar
  11. 11.
    Kencl, L., Boudec, J.Y.L.: Adaptive load sharing for network processors. IEEE ACM Transactions on Networking 16, 293–306 (2008)CrossRefGoogle Scholar
  12. 12.
    Chen, B., Morris, R.: Flexible control of parallelism in a multiprocessor PC router. In: USENIX Annual Technical Conference, Berkeley, CA, pp. 333–346 (2001)Google Scholar
  13. 13.
    Iyer, S., McKeown, N.: Making parallel packet switches practical. In: Proceedings of IEEE INFOCOM 2001, pp. 1680–1687. IEEE, Los Alamitos (2001)Google Scholar
  14. 14.
    Banka, T., Bare, A.A., Jayasumana, A.P.: Metrics for degree of reordering in packet sequences. In: LCN, pp. 333–342. IEEE Computer Society, Los Alamitos (2002)Google Scholar
  15. 15.
    SoCLib Consortium: The SoCLib project: An integrated system-on-chip modelling and simulation platform. Technical report, CNRS (2003),
  16. 16.
    VSI Alliance: Virtual Component Interface Standard (OCB 2 2.0). Technical report, VSI Alliance (2001)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Daniela Genius
    • 1
  • Alix Munier Kordon
    • 1
  • Khouloud Zine el Abidine
    • 1
  1. 1.Laboratoire LIP6Université Pierre et Marie CurieParisFrance

Personalised recommendations