Throughput Considerations of Fault-Tolerant Routing in Network-on-Chip

  • Arshin Rezazadeh
  • Mahmood Fathy
Part of the Communications in Computer and Information Science book series (CCIS, volume 40)


Fault-tolerant routing is the ability to survive beyond the failure of individual components and usually uses several virtual channels (VCs) to pass faulty nodes or links. A well-known wormhole-switched routing algorithm for 2-D mesh interconnection network, f-cube3, uses three virtual channels to pass faulty blocks such as f-ring and f-chain, while only one virtual channel is used when a message does not encounter any fault. One of the key issues in the design of NoCs is the development of an efficient communication system to provide high throughput and low latency interconnection networks. We have evaluated a new fault-tolerant routing algorithm based on f-cube3 as a solution to increase the throughput of physical links more than f-cube3 with lower message delay which uses less number of VCs compared to f-cube3 by reducing required virtual channels to two. Simulation of both f-cube3 and improved algorithm, if-cube2 (improved f-cube2) for the same conditions presented. As the simulation results show, if-cube2 has a higher performance than f-cube3 algorithm even with one less VC. The results also show that our algorithm has less exist packets in network and better performance with 100% traffic load in Network-on-Chip.


Network-on-Chip throughput performance interconnection fault-tolerant routing wormhole switching virtual channel deterministic routing 


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  1. 1.
    Ali, M., Welzl, M., Zwicknagl, M., Hellebrand, S.: Considerations for fault-tolerant network on chips. In: The 17th International Conference on Microelectronics, December 13-15, pp. 178–182 (2005)Google Scholar
  2. 2.
    Banerjee, N., Vellanki, P., Chatha, K.S.: A Power and Performance Model for Network-on-Chip Architectures. In: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), February 16-20, vol. 2, pp. 1250–1255 (2004)Google Scholar
  3. 3.
    Benini, L., De Micheli, G.: Networks on chips: A new SoC paradigm. IEEE Computer, 70–78 (January 2002)Google Scholar
  4. 4.
    Boppana, R.V., Chalasani, S.: Fault-tolerant wormhole routing algorithms for mesh networks. IEEE Trans. Computers 44(7), 848–864 (1995)CrossRefGoogle Scholar
  5. 5.
    Dao, B.V., Duato, J., Yalamanchili, S.: Dynamically configurable message flow control for fault-tolerant routing. IEEE Transactions on Parallel and Distributed Systems 10(1), 7–22 (1999)CrossRefGoogle Scholar
  6. 6.
    Dally, W.J.: Virtual channel flow control. IEEE TPDS 3(2), 194–205 (1992)Google Scholar
  7. 7.
    Dally, W.J., Seitz, C.L.: Deadlock-free message routing in multiprocessor interconnection networks. IEEE Trans. Computers 36(5), 547–553 (1987)CrossRefGoogle Scholar
  8. 8.
    Dally, W.J., Towles, B.: Principles and practices of interconnection networks. Morgan Kaufman Publishers, San Francisco (2004)Google Scholar
  9. 9.
    Dally, W.J., Towles, B.: Route packets, not wires: On-chip interconnection networks. In: Proceedings. Design Automation Conference, Las Vegas, NV, USA, June 18-21, pp. 684–689 (2001)Google Scholar
  10. 10.
    Duato, J., Yalamanchili, S., Ni, L.: Interconnection networks: An engineering approach. Morgan Kaufmann, San Francisco (2003)Google Scholar
  11. 11.
    Guerrier, P., Greiner, A.: A generic architecture for on-chip packet-switched interconnections. In: Proceedings. Design Automation and Test in Europe Conference and Exhibition, Paris, France, March 27-30, pp. 250–256 (2000)Google Scholar
  12. 12.
    Hemani, A., Jantsch, A., Kumar, S., Postula, A., Oberg, J., Millberg, M., Lindqvist, D.: Network on chip: an architecture for billion transistor era. In: IEEE NorChip Conf., November 2000, pp. 120–124 (2000)Google Scholar
  13. 13.
    Kiasari, A.E., Sarbazi-Azad, H.: Analytic performance comparison of hypercubes and star graphs with implementation constraints. Journal of Computer and System Sciences 74(6), 1000–1012 (2008)CrossRefGoogle Scholar
  14. 14.
    Kumar, S., Jantsch, A., Millberg, M., Oberg, J., Soininen, J., Forsell, M., Tiensyrj, K., Hemani, A.: A network on chip architecture and design methodology. In: Symposium on VLSI, April 2002, pp. 117–124 (2002)Google Scholar
  15. 15.
    Lap-Fai, L., Chi-Ying, T.: Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems. In: DAC 2006, San Francisco, California, USA (July 2006)Google Scholar
  16. 16.
    Matsutani, H., Koibuchi, M., Yamada, Y., Jouraku, A., Amano, H.: Non-minimal routing strategy for application-specific networks-on-chips. In: ICPP 2005, International Conference Workshops on Parallel Processing, June 14-17, pp. 273–280 (2005)Google Scholar
  17. 17.
    Rezazadeh, A., Fathy, M., Hassanzadeh, A.: If-cube3: an improved fault-tolerant routing algorithm to achieve less latency in NoCs. In: IACC 2009, IEEE International Advanced Computing Conference, March 6-7, pp. 278–283 (2009)Google Scholar
  18. 18.
    Rezazadeh, A., Fathy, M., Rahnavard, G.A.: An enhanced fault-tolerant routing algorithm for mesh network-on-chip. In: ICESS 2009, 6th International Conference on Embedded Software and Systems, May 25-27, pp. 505–510 (2009)Google Scholar
  19. 19.
    Srinivasan, K., Chatha, K.S.: A technique for low energy mapping and routing in network-on-chip architectures. In: ISLPED 2005, San Diego, California, USA, August 8-10, pp. 387–392 (2005)Google Scholar
  20. 20.
    Sui, P.H., Wang, S.D.: An improved algorithm for fault-tolerant wormhole routing in meshes. IEEE Trans. on Computers 46(9), 1040–1042 (1997)CrossRefGoogle Scholar
  21. 21.
    Yang, S.G., Li, L., Xu, Y., Zhang, Y.A., Zhang, B.: A power-aware adaptive routing scheme for network on a chip. In: ASICON 2007, 7th International Conference on ASIC, October 22-25, pp. 1301–1304 (2007)Google Scholar

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© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Arshin Rezazadeh
    • 1
  • Mahmood Fathy
    • 1
  1. 1.Department of Computer EngineeringIran University of Science and TechnologyTehranIran

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