Efficient K-Means VLSI Architecture for Vector Quantization

  • Hui-Ya Li
  • Wen-Jyi Hwang
  • Chih-Chieh Hsu
  • Chia-Lung Hung
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5575)


A novel hardware architecture for k-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on a FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for k-means design.


Vector Quantization Pipeline Stage Training Vector VLSI Architecture FPGA Device 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Hui-Ya Li
    • 1
  • Wen-Jyi Hwang
    • 1
  • Chih-Chieh Hsu
    • 1
  • Chia-Lung Hung
    • 1
  1. 1.Department of Computer Science and Information EngineeringNational Taiwan Normal UniversityTaipeiTaiwan

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