Abstract
Data cache is a commodity in modern microprocessor systems. It is a fact that the size of data caches keeps growing up, however, the increase in application size goes faster. As a result, it is usually not possible to store the complete working set in the cache memory.
This paper proposes an approach that allows the data access of some load/store instructions to bypass the cache memory. In this case, the cache space can be reserved for storing more frequently reused data. We implemented an analysis algorithm to identify the specific instructions and a simulator to model the novel cache architecture. The approach was verified using applications from MediaBench/MiBench benchmark suite and for all except one application we achieved huge gains in performance.
Keywords
- Cache optimization
- simulation
- architecture design
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Tao, J., Hillenbrand, D., Marten, H. (2009). Instruction Hints for Super Efficient Data Caches. In: Allen, G., Nabrzyski, J., Seidel, E., van Albada, G.D., Dongarra, J., Sloot, P.M.A. (eds) Computational Science – ICCS 2009. ICCS 2009. Lecture Notes in Computer Science, vol 5545. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-01973-9_76
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DOI: https://doi.org/10.1007/978-3-642-01973-9_76
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-01972-2
Online ISBN: 978-3-642-01973-9
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