Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm

  • Jaeyoung Yi
  • Karam Park
  • Joonseok Park
  • Won W. Ro
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5453)


As the need for information security increases in our everyday life, the job of encoding/decoding for secure information delivery becomes a critical issue in data network systems. High-speed data encoding for cryptography is required especially when sending a large amount of important data with high-speed transmission. In order to accomplish the procedure more efficiently, previous research focused on implementing existing algorithms using hardware accelerators. In this paper, we discuss and propose the FPGA implementation of the SEED block cipher algorithm, which is a Korean national industrial association standard for secured systems. Our implementation, which is written in Verilog HDL, is synthesized and tested on a Virtex-V XC5LX110T FPGA device. Our results show that the proposed fully pipelined design achieves high throughput and can support as high as 6.4 Gbps network speed. Compared to a full software implementation on the Intel Core 2 Duo 2.53 GHz processor, our implementation provides 34 times higher performance in terms of encoding/decoding throughput.


Field Programmable Gate Arrays (FPGA) Block Cipher Algorithm Cryptography SEED 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Jaeyoung Yi
    • 1
  • Karam Park
    • 1
  • Joonseok Park
    • 2
  • Won W. Ro
    • 1
  1. 1.School of Electrical and Electronic EngineeringYonsei UniversitySeoulKorea
  2. 2.College of Information TechnologyInha UniversitySeoulKorea

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