Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm
As the need for information security increases in our everyday life, the job of encoding/decoding for secure information delivery becomes a critical issue in data network systems. High-speed data encoding for cryptography is required especially when sending a large amount of important data with high-speed transmission. In order to accomplish the procedure more efficiently, previous research focused on implementing existing algorithms using hardware accelerators. In this paper, we discuss and propose the FPGA implementation of the SEED block cipher algorithm, which is a Korean national industrial association standard for secured systems. Our implementation, which is written in Verilog HDL, is synthesized and tested on a Virtex-V XC5LX110T FPGA device. Our results show that the proposed fully pipelined design achieves high throughput and can support as high as 6.4 Gbps network speed. Compared to a full software implementation on the Intel Core 2 Duo 2.53 GHz processor, our implementation provides 34 times higher performance in terms of encoding/decoding throughput.
KeywordsField Programmable Gate Arrays (FPGA) Block Cipher Algorithm Cryptography SEED
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- 1.Federal Information Processing Standards Publication 46-3: Data Encryption Standard (1999)Google Scholar
- 2.Federal Information Processing Standards Publication 197: Advanced Encryption Standard (2001)Google Scholar
- 3.Miyaguchi, S.: The FEAL Cipher Family. In: Menezes, A., Vanstone, S.A. (eds.) CRYPTO 1990. LNCS, vol. 537, pp. 627–637. Springer, Heidelberg (1991)Google Scholar
- 4.Korea Information Security Agency: A Design and Analysis of 128-bit Symmetric Block Cipher (SEED) (1999)Google Scholar
- 5.Beuchat, J.L.: FPGA Implementations of the RC6 Block Cipher. In: Proc. of the 13th Int’l Conference on Field-Programmable Logic and its Applications, Portugal (2003)Google Scholar
- 6.NESSIE: NESSIE Project Announces Final Selection of Crypto Algorithms, IST-199-12324 (2003)Google Scholar
- 7.Information-Technology Promotion Agency, Japan, CRYPTREC Report (2002)Google Scholar
- 9.Zambreno, J., Nguyen, D., Choudhary, A.: Exploring Area/Delay Tradeoffs in an AES FPGA Implementation. In: Proc of Int’l Conference on Field-Programmable Logic and its Applications, Belguim (2004)Google Scholar
- 10.Rouvroy, G., Standaert, F.X.: Efficient FPGA Implementation of Block Cipher MISTY1. In: Proc of IEEE International Parallel & Distributed Processing Symposium, France (2003)Google Scholar
- 12.Seo, Y.H., Kim, I.H., Kim, D.W.: Hardware Implementation of 128-bit Symmetric Cipher SEED. In: Proc. of the Second IEEE Asia Pacific Conference on AP-SIC 2000, pp. 183–186 (2000)Google Scholar