Abstract
Although the H.264 Deblocking Filter process is a relatively small piece of code in a software implementation, profile results shows it cost about a third of the total CPU time in the decoder. This work presents a high performance architecture for implementing a H.264 Deblocking Filter IP that can be used either in the decoder or in the encoder as a hardware accelerator for a processor or embedded in a full-hardware codec. A developed IP using the proposed architecture support multiple high definition processing flows in real-time.
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Rosa, V., Susin, A., Bampi, S. (2009). A High Performance H.264 Deblocking Filter. In: Wada, T., Huang, F., Lin, S. (eds) Advances in Image and Video Technology. PSIVT 2009. Lecture Notes in Computer Science, vol 5414. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-92957-4_83
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DOI: https://doi.org/10.1007/978-3-540-92957-4_83
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-92956-7
Online ISBN: 978-3-540-92957-4
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