Abstract
This paper presents the design of an FPGA based real time video display size resolution conversion for QCIF to VGA. The architecture is based on a pre-computed memory mapping that facilitates reduction in memory size and latency. The scheme has been realized for real time resolution conversion of a QCIF video at 30 fps. The memory requirement has been reduced to 400 KB which is significantly lower than an earlier hardware based scheme [2] where memory used was nearly 5 MB. The results have been validated on Xilinx Spartan-2E FPGA running at 100MHz. The area of complete design is around 66K gates including input and output memory.
Chapter PDF
References
Lehmann, T.M.: Survey: Interpolation Methods in Medical Image Processing. IEEE transactions on medical imaging 18(11) (November 1999)
Aho, E., Vanne, J., Hämäläinen, T.D., Kuusilinna, K.: Block-Level Parallel Processing for Scaling Evenly Divisible Images. IEEE Transactions on circuits and systems 52(12), 2717–2725 (2005)
Ramachanran, S., Srinivasan, S.: Design and FPGA implementation of an MPEG based video scalar with reduced on-chip memory utilization. Journal of Systems Architecture 51, 435–450 (2005)
Aurelio, M., Arias-Estrada, M.O.: Real Time FPGA Based Architecture for Bi-cubic Interpolation: An Application for Digital Image Scaling. In: Proceedings of International Conference on Reconfigurable Computing and FPGAs, September 28-30 (2005)
Lin, T.-C., Truong, T.-K.: DCT-Based Image Codec Embedded Cubic Spline Interpolation with Optimal Quantization. In: Proceedings of IEEE international Symposium on Multimedia, pp. 2746–2749 (September 2006)
Wang, L., Wang, Q.: A fast Intra Mode Decision Algorithm for MPEG-2 to H.264 Video Transcoding. In: Proceedings of IEEE 10th International Symposium on Consumer Electronic, pp. 1–5 (December 2006)
Standards documents MPEG-1: Coding of moving pictures and associated audio for digital storage media at up to 1.5 Mbps. ISO/IEC 11172-2: video (November 1991)
Wanrong, L., Bushmitch, D.: Design and implementation of a high quality DV50-MPEG2 software transcoder. In: International Conference on Consumer Electronics, pp. 142–143 (June 2002)
Kim, C.-H., Seong, S.-M., Lee, J.-A., Kim, L.-S.: Winscale: An Image-Scaling Algorithm Using an Area Pixel Model. IEEE Transactions on Circuits and Systems for Video Technology 13(6), 549–553 (2003)
Aho, E., Vanne, J., Hämäläinen, T.D., Kuusilinna, K.: Configurable Implementation of Parallel Memory Based Real-time Video Downscaler. Microprocessors and Microsystems 31(5), 283–292 (2007)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2009 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Khan, A.A., Masud, S. (2009). Memory Efficient VLSI Architecture for QCIF to VGA Resolution Conversion. In: Wada, T., Huang, F., Lin, S. (eds) Advances in Image and Video Technology. PSIVT 2009. Lecture Notes in Computer Science, vol 5414. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-92957-4_72
Download citation
DOI: https://doi.org/10.1007/978-3-540-92957-4_72
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-92956-7
Online ISBN: 978-3-540-92957-4
eBook Packages: Computer ScienceComputer Science (R0)