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Memory Efficient VLSI Architecture for QCIF to VGA Resolution Conversion

  • Asmar A. Khan
  • Shahid Masud
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5414)

Abstract

This paper presents the design of an FPGA based real time video display size resolution conversion for QCIF to VGA. The architecture is based on a pre-computed memory mapping that facilitates reduction in memory size and latency. The scheme has been realized for real time resolution conversion of a QCIF video at 30 fps. The memory requirement has been reduced to 400 KB which is significantly lower than an earlier hardware based scheme [2] where memory used was nearly 5 MB. The results have been validated on Xilinx Spartan-2E FPGA running at 100MHz. The area of complete design is around 66K gates including input and output memory.

Keywords

Display resolution conversion Image-scaling VLSI architecture FPGA QCIF VGA 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Asmar A. Khan
    • 1
  • Shahid Masud
    • 1
  1. 1.Department of Computer Science and EngineeringLahore University of Management SciencesLahorePakistan

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