Memory Efficient VLSI Architecture for QCIF to VGA Resolution Conversion

  • Asmar A. Khan
  • Shahid Masud
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5414)


This paper presents the design of an FPGA based real time video display size resolution conversion for QCIF to VGA. The architecture is based on a pre-computed memory mapping that facilitates reduction in memory size and latency. The scheme has been realized for real time resolution conversion of a QCIF video at 30 fps. The memory requirement has been reduced to 400 KB which is significantly lower than an earlier hardware based scheme [2] where memory used was nearly 5 MB. The results have been validated on Xilinx Spartan-2E FPGA running at 100MHz. The area of complete design is around 66K gates including input and output memory.


Display resolution conversion Image-scaling VLSI architecture FPGA QCIF VGA 


  1. 1.
    Lehmann, T.M.: Survey: Interpolation Methods in Medical Image Processing. IEEE transactions on medical imaging 18(11) (November 1999)Google Scholar
  2. 2.
    Aho, E., Vanne, J., Hämäläinen, T.D., Kuusilinna, K.: Block-Level Parallel Processing for Scaling Evenly Divisible Images. IEEE Transactions on circuits and systems 52(12), 2717–2725 (2005)CrossRefGoogle Scholar
  3. 3.
    Ramachanran, S., Srinivasan, S.: Design and FPGA implementation of an MPEG based video scalar with reduced on-chip memory utilization. Journal of Systems Architecture 51, 435–450 (2005)CrossRefGoogle Scholar
  4. 4.
    Aurelio, M., Arias-Estrada, M.O.: Real Time FPGA Based Architecture for Bi-cubic Interpolation: An Application for Digital Image Scaling. In: Proceedings of International Conference on Reconfigurable Computing and FPGAs, September 28-30 (2005)Google Scholar
  5. 5.
    Lin, T.-C., Truong, T.-K.: DCT-Based Image Codec Embedded Cubic Spline Interpolation with Optimal Quantization. In: Proceedings of IEEE international Symposium on Multimedia, pp. 2746–2749 (September 2006)Google Scholar
  6. 6.
    Wang, L., Wang, Q.: A fast Intra Mode Decision Algorithm for MPEG-2 to H.264 Video Transcoding. In: Proceedings of IEEE 10th International Symposium on Consumer Electronic, pp. 1–5 (December 2006)Google Scholar
  7. 7.
    Standards documents MPEG-1: Coding of moving pictures and associated audio for digital storage media at up to 1.5 Mbps. ISO/IEC 11172-2: video (November 1991)Google Scholar
  8. 8.
    Wanrong, L., Bushmitch, D.: Design and implementation of a high quality DV50-MPEG2 software transcoder. In: International Conference on Consumer Electronics, pp. 142–143 (June 2002)Google Scholar
  9. 9.
    Kim, C.-H., Seong, S.-M., Lee, J.-A., Kim, L.-S.: Winscale: An Image-Scaling Algorithm Using an Area Pixel Model. IEEE Transactions on Circuits and Systems for Video Technology 13(6), 549–553 (2003)CrossRefGoogle Scholar
  10. 10.
    Aho, E., Vanne, J., Hämäläinen, T.D., Kuusilinna, K.: Configurable Implementation of Parallel Memory Based Real-time Video Downscaler. Microprocessors and Microsystems 31(5), 283–292 (2007)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Asmar A. Khan
    • 1
  • Shahid Masud
    • 1
  1. 1.Department of Computer Science and EngineeringLahore University of Management SciencesLahorePakistan

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