Skip to main content
SpringerLink
Log in

Combinatorial Problems in Chip Design

  • Chapter
Building Bridges

Part of the book series: Bolyai Society Mathematical Studies ((BSMS,volume 19))

Abstract

The design of very large scale integrated (VLSI) chips is an exciting area of applying mathematics, posing constantly new challenges.

We present some important and challenging open problems in various areas of chip design. Although the problems are motivated by chip design, they are formulated mathematically; understanding and solving them does not require any knowledge of chip design. We give some partial results and argue why a full resolution of one of the problems could result in an advance of the state of the art in algorithms for chip design.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. C. Albrecht, Global routing by new approximation algorithms for multicommodity flow, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 20 (2001), 622–632.

    Article  Google Scholar 

  2. C. Albrecht, Efficient incremental clock latency scheduling for large circuits, Design, Automation and Test in Europe, Proceedings, IEEE (2006), 1091–1096.

    Google Scholar 

  3. C. Albrecht, B. Korte, J. Schietke and J. Vygen, Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip, Discrete Applied Mathematics, 123 (2002), 103–127.

    Article  MATH  MathSciNet  Google Scholar 

  4. N. Alon and Y. Azar, On-line Steiner trees in the Euclidean plane, Discrete and Computational Geometry, 10 (1993), 113–121.

    Article  MATH  MathSciNet  Google Scholar 

  5. C. Ambühl, M. Mastrolilli and O. Svensson, Inapproximability results for sparsest cut, optimal linear arrangement, and precedence constrained scheduling, Proceedings of the 48th Annual IEEE Symposium on Foundations of Computer Science (2007), 329–337.

    Google Scholar 

  6. C. Bartoschek, S. Held, D. Rautenbach and J. Vygen, Efficient generation of short and fast repeater tree topologies, Proceedings of the International Symposium on Physical Design (2006), 120–127.

    Google Scholar 

  7. D. Bienstock and G. Iyengar, Solving fractional packing problems in O *(1/e) iterations, SIAM Journal on Computing, 35 (2006), 825–854.

    Article  MATH  MathSciNet  Google Scholar 

  8. K. D. Boese, A. B. Kahng, B. A. McCoy and G. Robins, Rectilinear Steiner trees with minimum Elmore delay, Proceedings of the 31st IEEE/ACM Design Automation Conference (1994), 381–386.

    Google Scholar 

  9. U. Brenner, M. Struzyna and J. Vygen, BonnPlace: placement of leading-edge chips by advanced combinatorial algorithms, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, to appear

    Google Scholar 

  10. U. Brenner and J. Vygen, Worst-case ratios of networks in the rectilinear plane, Networks, 38 (2001), 126–139.

    Article  MATH  MathSciNet  Google Scholar 

  11. U. Brenner and J. Vygen, Legalizing a placement with minimum total movement, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 23 (2004), 1597–1613.

    Article  Google Scholar 

  12. U. Brenner and J. Vygen, Analytical methods in VLSI placement, in: Handbook of Algorithms for VLSI Physical Design Automation (C. J. Alpert, D. P. Mehta, S. S. Sapatnekar, eds.), Taylor and Francis (2008).

    Google Scholar 

  13. A. V. Cabot, R. L. Francis and A. M. Stary, A network flow solution to a rectilinear distance facility location problem, AIIE Transactions, 2 (1970), 132–141.

    Google Scholar 

  14. Y.-C. Chang, Y.-W. Chang, G.-M. Wu and S.-W. Wu, B*-trees: a new representation for non-slicing floorplans, Proceedings of the 37th ACM/IEEE Design Automation Conference (2000), 458–463.

    Google Scholar 

  15. M. Charikar, M. Hajiaghayi, H. Karloff and S. Rao, ℓ2 2 spreading metrics for vertex ordering problems, Proceedings of the 17th ACM-SIAM Symposium on Discrete Algorithms (2006), 1018–1027.

    Google Scholar 

  16. J. Cong, L. He, C.-K. Koh and P. H. Madden, Performance optimization of VLSI interconnect layout, Integration, the VLSI Journal, 21 (1996), 1–94.

    Article  MATH  Google Scholar 

  17. E. W. Dijkstra, A note on two problems in connexion with graphs, Numerische Mathematik, 1 (1959), 269–271.

    Article  MATH  MathSciNet  Google Scholar 

  18. W. C. Elmore, The transient response of damped linear networks with particular regard to wide-band amplifiers, Journal of Applied Physics, 19 (1948), 55–63.

    Article  Google Scholar 

  19. G. Even, J. Naor, S. Rao and B. Schieber, Divide-and-conquer approximation algorithms via spreading metrics, Journal of the ACM, 47 (2000), 585–616.

    Article  MathSciNet  Google Scholar 

  20. U. Feige and J. R. Lee, An improved approximation ratio for the minimum linear arrangement problem, Information Processing Letters, 101 (2007), 26–29.

    Article  MATH  MathSciNet  Google Scholar 

  21. V. Feldman, Hardness of approximate two-level logic minimization and PAC learning with membership queries, Proceedings of the 38th Annual ACM Symposium on the Theory of Computing (2006), 363–372.

    Google Scholar 

  22. N. Garg and J. Könemann, Faster and simpler algorithms for multicommodity flow and other fractional packing problems, SIAM Journal on Computing, 37 (2007), 630–652.

    Article  MATH  MathSciNet  Google Scholar 

  23. M. D. Grigoriadis and L. D. Khachiyan, Coordination complexity of parallel pricedirective decomposition, Mathematics of Operations Research, 21 (1996), 321–340.

    Article  MATH  MathSciNet  Google Scholar 

  24. M. Grötschel, L. Lovász and A. Schrijver, Geometric Algorithms and Combinatorial Optimization, Springer, Berlin (1988).

    MATH  Google Scholar 

  25. P. N. Guo, C.-K. Cheng and T. Yoshimura, An O-tree representation of nonslicing floorplan and its applications, Proceedings of the 36th ACM/IEEE Design Automation Conference (1999), 268–273.

    Google Scholar 

  26. R. H. Güting, An optimal contour algorithm for iso-oriented rectangles, Journal of Algorithms, 5 (1984), 303–326.

    Article  MATH  MathSciNet  Google Scholar 

  27. R. H. Güting, Optimal divide-and-conquer to compute measure and contour for a set of iso-oriented rectangles, Acta Informatica, 21 (1984), 271–291.

    Article  MATH  MathSciNet  Google Scholar 

  28. S. Held, Algorithmen für Potential-Balancierungs-Probleme und Anwendungen im VLSI-Design, Diploma thesis, University of Bonn (2001).

    Google Scholar 

  29. S. Held, B. Korte, J. Maßberg, M. Ringe and J. Vygen, Clock scheduling and clocktree construction for high performance ASICs, Proceedings of the IEEE International Conference on Computer-Aided Design (2003), 232–239.

    Google Scholar 

  30. S. Held, B. Korte, D. Rautenbach and J. Vygen, Combinatorial optimization in VLSI design, in: Combinatorial Optimization: Methods and Applications (V. Chvátal, N. Sbihi, eds.), IOS Press, to appear.

    Google Scholar 

  31. T. Ibaraki and K. Nakamura, Packing problems with soft rectangles, in: Hybrid Metaheuristics; Proceedings of the 3rd International Workshop on Hybrid Metaheuristics (HM 2006); LNCS 4030 (F. Almeida et al., eds.), Springer, Berlin (2006), pp. 13–27.

    Chapter  Google Scholar 

  32. K. Jansen and H. Zhang, Approximation algorithms for general packing problems and their application to the multicast congestion problem, Mathematical Programming, 114 (2008), 183–206.

    Article  MATH  MathSciNet  Google Scholar 

  33. V. Kabanets and J.-Y. Cai, Circuit minimization problem, Proceedings of the 32nd Annual ACM Symposium on the Theory of Computing, (2000), 73–79.

    Google Scholar 

  34. T. Kadodi, Steiner routing based on Elmore delay model for minimizing maximum propagation delay, Master’s Thesis, Japan Advanced Institute of Science and Technology (1999).

    Google Scholar 

  35. A. B. Kahng and G. Robins, On Optimal Interconnections for VLSI, Kluwer Academic Publishers, Boston (1995).

    MATH  Google Scholar 

  36. [36] B. Korte, D. Rautenbach and J. Vygen, BonnTools: mathematical innovation for layout and timing closure of systems on a chip, Proceedings of the IEEE, 95 (2007), 555–572.

    Article  Google Scholar 

  37. B. Korte and J. Vygen, Combinatorial Optimization: Theory and Algorithms. Fourth Edition, Springer, Berlin (2008).

    Google Scholar 

  38. W. J. Masek, Some NP-complete set covering problems, Unpublished manuscript, M.I.T., Cambridge (1978).

    Google Scholar 

  39. J. Maßberg and J. Vygen, Approximation algorithms for a facility location problem with service capacities, ACM Transactions on Algorithms, to appear. A preliminary extended abstract appeared in: Approximation, Randomization and Combinatorial Optimization; Proceedings of the 8th International Workshop on Approximation Algorithms for Combinatorial Optimization Problems (APPROX 2005); LNCS 3624 (C. Chekuri, K. Jansen, J. D. P. Rolim, L. Trevisan, eds). Springer, Berlin (2005), pp. 158–169.

    Google Scholar 

  40. D. Müller, Optimizing yield in global routing, Proceedings of the IEEE International Conference on Computer-Aided Design (2006), 480–486.

    Google Scholar 

  41. D. Müller and J. Vygen, Faster min-max resource sharing and applications, manuscript, in preparation.

    Google Scholar 

  42. H. Murata, K. Fujiyoshi, S. Nakatake and Y. Kajitani, Rectangle-packing-based module placement, Proceedings of the IEEE International Conference on Computer-Aided Design (1995), 472–479.

    Google Scholar 

  43. J. B. Orlin, A faster strongly polynomial minimum cost flow algorithm, Operations Research, 41 (1993), 338–350.

    Article  MATH  MathSciNet  Google Scholar 

  44. S. Peyer, Elmore-Delay-optimale Steinerbäume im VLSI-Design. Diploma thesis, University of Bonn (2000).

    Google Scholar 

  45. S. Peyer, D. Rautenbach and J. Vygen, A generalization of Dijkstra’s shortest path algorithm with applications to VLSI routing. Report No. 06964-OR, Research Institute for Discrete Mathematics, University of Bonn (2006).

    Google Scholar 

  46. S. A. Plotkin, D. B. Shmoys and É. Tardos, Fast approximation algorithms for fractional packing and covering problems, Mathematics of Operations Research, 2 (1995), 257–301.

    Article  MathSciNet  Google Scholar 

  47. I. Pohl, Bi-directional search, Machine Intelligence, 6 (1971), 124–140.

    MathSciNet  Google Scholar 

  48. M. Queyranne, Performance ratio of polynomial heuristics for triangle inequality quadratic assignment problems, Operations Research Letters, 4 (1986), 231–234.

    Article  MATH  MathSciNet  Google Scholar 

  49. D. Rautenbach, C. Szegedy and J. Werber, Asymptotically optimal Boolean circuits for functions of the form g n −1(g n −2(…g 3(g 2(g 1(x 1, x 2), x 3), x 4) …, x n −1), x n ). Report No. 03931, Research Institute for Discrete Mathematics, University of Bonn (2003).

    Google Scholar 

  50. F. Rubin, The Lee path connection algorithm, IEEE Transactions on Computers, 23 (1974), 907–914.

    Article  MATH  Google Scholar 

  51. M. Solomon and R. A. Finkel, A note on enumerating binary trees, Journal of the ACM, 27 (1980), 3–5.

    Article  MathSciNet  Google Scholar 

  52. D. A. Spielman, Spectral graph theory and its applications, Proceedings of the 48th Annual IEEE Symposium on Foundations of Computer Science (2007), 29–38.

    Google Scholar 

  53. T. Takahashi, A new encoding scheme for rectangle packing problem, Proceedings of the Asia and South Pacific Design Automation Conference (2000), 175–178.

    Google Scholar 

  54. J. Vygen, Algorithms for detailed placement of standard cells, Design, Automation and Test in Europe, Proceedings, IEEE (1998), 321–324.

    Google Scholar 

  55. J. Vygen, Near-optimum global routing with coupling, delay bounds, and power consumption, in: Integer Programming and Combinatorial Optimization; Proceedings of the 10th International IPCO Conference; LNCS 3064 (G. Nemhauser, D. Bienstock, eds.), Springer, Berlin (2004), pp. 308–324.

    Google Scholar 

  56. J. Vygen, Slack in static timing analysis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25 (2006), 1876–1885.

    Article  Google Scholar 

  57. J. Vygen, New theoretical results on quadratic placement, Integration, the VLSI Journal, 40 (2007), 305–314.

    Article  Google Scholar 

  58. N. Young, Randomized rounding without solving the linear program, Proceedings of the 6th Annual ACM-SIAM Symposium on Discrete Algorithms (1995), 170–178.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Research Institute for Discrete Mathematics, University of Bonn, Lennéstr. 2, 53113, Bonn, Germany

    Bernhard Korte & Jens Vygen

Authors
  1. Bernhard Korte
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Jens Vygen
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Konrad-Zuse-Zentrum für Informationstechnik Berlin (ZIB), Takustr. 7, 14195, Berlin, Germany

    Martin Grötschel

  2. Hungarian Academy of Sciences, Alfréd Rényi Institute of Mathematics, Reáltanoda u. 13-15, Budapest, 1053, Hungary

    Gyula O. H. Katona  & Gábor Sági  & 

Rights and permissions

Reprints and permissions

Copyright information

© 2008 János Bolyai Mathematical Society and Springer-Verlag

About this chapter

Cite this chapter

Korte, B., Vygen, J. (2008). Combinatorial Problems in Chip Design. In: Grötschel, M., Katona, G.O.H., Sági, G. (eds) Building Bridges. Bolyai Society Mathematical Studies, vol 19. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-85221-6_12

Download citation

Publish with us

Policies and ethics

Search

Navigation