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On Formal Equivalence Verification of Hardware

  • Zurab Khasidashvili
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5010)

Abstract

When modeling the logic functionality, hardware can be viewed as a Finite State Machine (FSM) [7]. The power-up state of hardware cannot be determined uniquely, therefore the FSM modeling the hardware does not have an initial state (or a set of initial states). Instead, it has a set of legal operation states, and it must be brought into this set of operation states from any power-up state by a reboot sequence.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Zurab Khasidashvili
    • 1
  1. 1.Formal Technology and Logic GroupIntel CorporationHaifaIsrael

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