Abstract
Software bugs can cause tremendous financial loss and are a serious threat to life or physical condition in safety-critical areas. Formal software verification with theorem provers aims at ensuring that no errors are present but is too expensive to be employed for full-scale systems. We show that these costs can be reduced significantly by reusing proofs and by the checker approach. We demonstrate the applicability of our approach by a case study checking the correctness of the scheduler of the popular GCC compiler for a VLIW processor where we indeed found an error.
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Gesellensetter, L., Glesner, S., Salecker, E. (2008). Formal Verification with Isabelle/HOL in Practice: Finding a Bug in the GCC Scheduler. In: Leue, S., Merino, P. (eds) Formal Methods for Industrial Critical Systems. FMICS 2007. Lecture Notes in Computer Science, vol 4916. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-79707-4_8
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DOI: https://doi.org/10.1007/978-3-540-79707-4_8
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