Abstract
Flash memories are nonvolatile memories, i.e., they are able to retain information even if the power supply is switched off. These memories are characterized by the fact that the erase operation (the writing of logic “1”) has to be performed at the same time on a group of cells called a sector or block; on the other hand, the program operation (the writing of logic “0”) is a selective operation during which a single cell is programmed. The fact that the erase can be executed only on an entire sector allows one to design the matrix in a compact shape and therefore in a very competitive size, from an economic point of view. Depending on how the cells are organized in the matrix, it is possible to distinguish between NAND Flash memories and NOR Flash memories. The main electric characteristics are reported below.
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References
Campardo G, Micheloni R, Novosel D (2005) VLSI-design of nonvolatile memories. Springer series in advanced microelectronics
Elmhurst D et al. (2003) A 1.8V 128Mb 125MHz multi-level cell flash memory with flexible read while write. ISSCC Dig Tech Pap 286–287
Jung TS (1996) A 3.3-V 128-Mb multilevel NAND flash memory for mass storage applications. ISSCC Dig Tech Pap 32–33
Lenzlinger M, Show EH (1969) Fowler-Nordheim tunnelling into thermally grown SiO2. IEDM Tech Dig 40:273–283
Hu C (1993) Future CMOS scaling and reliability. P IEEE 81:682–689
Kenney S et al. (1992) Complete transient simulation of flash EEPROM devices. IEEE T Electron Dev 39:2750–2757
Bez R et al. (2003) Introduction to flash memory. P IEEE 91:554–568
Cappelletti P et al. (eds) (1999) Flash memories. Kluwer, Norwell, MA
Pavan P, Bez R, Olivo P, Zanoni E (1997) Flash memory cells—an overview. P IEEE 85: 1248–1271
Umezawa A et al. (1992) A 5V-only operation 0.6-μm flash EEPROM with row decoder scheme in triple-well structure. IEEE J Solid-St Circ 27:1540–1546
Motta I, Ragone G, Khouri O, Torelli G, Micheloni R (2003) High-voltage management in single-supply CHE NOR-type flash memories. P IEEE 91:554–568
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Crippa, L., Micheloni, R., Motta, I., Sangalli, M. (2008). Nonvolatile Memories: NOR vs. NAND Architectures. In: Micheloni, R., Campardo, G., Olivo, P. (eds) Memories in Wireless Systems. Signals and Communication Technology. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-79078-5_2
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DOI: https://doi.org/10.1007/978-3-540-79078-5_2
Publisher Name: Springer, Berlin, Heidelberg
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