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Motion Compensation Hardware Accelerator Architecture for H.264/AVC

  • Bruno Zatt
  • Valter Ferreira
  • Luciano Agostini
  • Flávio R. Wagner
  • Altamiro Susin
  • Sergio Bampi
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4872)

Abstract

This work presents a new hardware acceleration solution for the H.264/AVC motion compensation process. A novel architecture is proposed to precede the luminance interpolation task, which responds by the highest computational complexity in the motion compensator. The accelerator module was integrated into the VHDL description of the MIPS Plasma processor, and its validation was accomplished by simulation. A performance comparison was made between a software implementation and a hardware accelerated one. This comparison indicates a reduction of 94% in processing time. The obtained throughput is enough to reach real time when decoding H.264/AVC Baseline Profile motion compensation for luminance at Level 3.

Keywords

Video Coding H.264/AVC MPEG-4 AVC Motion Compensation Hardware Acceleration 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Bruno Zatt
    • 1
  • Valter Ferreira
    • 1
  • Luciano Agostini
    • 2
  • Flávio R. Wagner
    • 1
  • Altamiro Susin
    • 3
  • Sergio Bampi
    • 1
  1. 1.Informatics Institute, Federal University of Rio Grande do Sul, Porto Alegre – RSBrazil
  2. 2.Informatics Department, Federal University of Pelotas, Pelotas – RSBrazil
  3. 3.Electrical Engineering Department, Federal University of Rio Grande do Sul, Porto Alegre – RSBrazil

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