Motion Compensation Hardware Accelerator Architecture for H.264/AVC

  • Bruno Zatt
  • Valter Ferreira
  • Luciano Agostini
  • Flávio R. Wagner
  • Altamiro Susin
  • Sergio Bampi
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4872)


This work presents a new hardware acceleration solution for the H.264/AVC motion compensation process. A novel architecture is proposed to precede the luminance interpolation task, which responds by the highest computational complexity in the motion compensator. The accelerator module was integrated into the VHDL description of the MIPS Plasma processor, and its validation was accomplished by simulation. A performance comparison was made between a software implementation and a hardware accelerated one. This comparison indicates a reduction of 94% in processing time. The obtained throughput is enough to reach real time when decoding H.264/AVC Baseline Profile motion compensation for luminance at Level 3.


Video Coding H.264/AVC MPEG-4 AVC Motion Compensation Hardware Acceleration 


  1. 1.
    JVT, Wiegand, T., Sullivan, G., Luthra, A.: Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec.H.264 ISO/IEC 14496-10 AVC). JVT-G050r1, Geneva (2003)Google Scholar
  2. 2.
    International Telecommunication Union.: Advanced Video Coding for Generic Audiovisual Services. ITU-T Recommendation H(264) (2005)Google Scholar
  3. 3.
    Wiegand, T., Schwarz, H., Joch, A., Kossentini, F., Sullivan, G.: Rate-constrained Coder Control and Comparison of Video Coding Standards. IEEE Transactions on Circuits and Systems for Video Technology 13, 688–703 (2003)CrossRefGoogle Scholar
  4. 4.
    International Telecommunication Union: Generic Coding of Moving Pictures and Associated Audio Information - Part 2. ITU-T Recommendation H(262) (1994)Google Scholar
  5. 5.
    International Organization For Standardization. Coding of Audio Visual Objects - Part 2 ISO/IEC 14496-2 - MPEG-4 Part 2 (1999)Google Scholar
  6. 6.
    Azevedo, A., Zatt, B., Agostini, L., Bampi, B.: Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV. In: IFIP International Conference on Very Large Scale Integration, VLSI SoC, Nice, France, pp. 52–57 (2006)Google Scholar
  7. 7.
    Wang, S.-Z., Lin, T.-A., Liu, T.-M., Lee, C.-Y.: A New Motion Compensation Design for H.264/AVC Decoder. In: International Symposium on Circuits and Systems. In: ISCAS, Kobe, Japan, pp. 4558–4561 (2005)Google Scholar
  8. 8.
    Chen, J.-W., Lin, C.-C., Guo, J.-I., Wang, J.-S.: Low Complexity Architecture Design of H.264 Predictive Pixel Compensator for HDTV Applications. In: Proc. 2006 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP, Toulouse, France, pp. 932–935 (2006)Google Scholar
  9. 9.
    OPENCORES.ORG (2007), Available from: URL:
  10. 10.
    Xilinx Inc. (2007), Availabe from:
  11. 11.
    H.264/AVC JM Reference Software (2007), Available from: URL:

Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Bruno Zatt
    • 1
  • Valter Ferreira
    • 1
  • Luciano Agostini
    • 2
  • Flávio R. Wagner
    • 1
  • Altamiro Susin
    • 3
  • Sergio Bampi
    • 1
  1. 1.Informatics Institute, Federal University of Rio Grande do Sul, Porto Alegre – RSBrazil
  2. 2.Informatics Department, Federal University of Pelotas, Pelotas – RSBrazil
  3. 3.Electrical Engineering Department, Federal University of Rio Grande do Sul, Porto Alegre – RSBrazil

Personalised recommendations