A Software Framework for Energy and Performance Tradeoff in Fixed-Priority Hard Real-Time Embedded Systems

  • Gang Zeng
  • Hiroyuki Tomiyama
  • Hiroaki Takada
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4808)


A dynamic energy performance scaling (DEPS) framework is proposed to save energy in fixed-priority hard real-time embedded systems. In this generalized framework, two existing technologies, i.e., dynamic hardware resource configuration (DHRC) and dynamic voltage frequency scaling (DVFS) can be combined for energy performance tradeoff. The problem of selecting the optimal hardware configuration and voltage/frequency parameters is formulated to achieve maximal energy savings and meet the deadline constraint simultaneously. Through a case study, the effectiveness of DEPS has been validated.


Early Deadline First Schedulability Test Instruction Cache Dynamic Voltage Scaling Deadline Constraint 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Pillai, P., Shin, K.G.: Real-Time Dynamic Voltage Scaling for Low-Power Embedded Operating Systems. In: Proc. ACM Symposium Operating Systems Principles, pp. 89–102 (2001)Google Scholar
  2. 2.
    Kim, W., Shin, D., Yun, H., Kim, J., Min, S.L.: Performance Comparison of Dynamic Voltage Scaling Algorithms for Hard Real-Time Systems. In: Proc. IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 219–228 (2002)Google Scholar
  3. 3.
    Saewong, S., Rajkumar, R.: Practical Voltage Scaling for Fixed-Priority RT-Systems. In: Proc. IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 106–114 (2003)Google Scholar
  4. 4.
    Cho, Y., Chang, N., Chakrabarti, C., Vrudhula, S.: High-Level Power Management of Embedded Systems with Application-Specific Energy Cost Functions. In: Proc. Design Automation Conference (DAC), pp. 568–573 (2006)Google Scholar
  5. 5.
    Choi, K., Soma, R., Pedram, M.: Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Tradeoff Based on the Ratio of Off-Chip Access to On-Chip Computation Times. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems 24(1), 18–28 (2005)CrossRefGoogle Scholar
  6. 6.
    Shin, D., Kim, J.: Intra-Task Voltage Scheduling on DVS-Enabled Hard Real-Time Systems. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems 24(10), 1530–1549 (2005)CrossRefGoogle Scholar
  7. 7.
    Yuan, W., Nahrstedt, K., Adve, S.V., Jones, D.L., Kravets, R.H.: GRACE-1: Cross-Layer Adaptation for Multimedia Quality and Battery Energy. IEEE Trans. Mobile Computing 5(7), 799–815 (2006)CrossRefGoogle Scholar
  8. 8.
    Albonesi, D.H., Balasubramonian, R., Dropsbo, S.G., et al.: Dynamically Tuning Processor Resources with Adaptive Processing. IEEE Computer, 49–58 (2003)Google Scholar
  9. 9.
    Huang, M., Renau, J., Torrellas, J.: Positional Adaptation of Processors: Application to Energy Reduction. In: Proc. IEEE International Symposium Computer Architecture, pp. 157–168 (2003)Google Scholar
  10. 10.
    Chaver, D., Pinuel, L., Prieto, M., Tirado, F., Huang, M.: Branch Prediction on Demand: An Energy-Efficient Solution. In: Proc. International Symposium on Low-Power Electronics and Design, pp. 390–395 (2003)Google Scholar
  11. 11.
    Albonesi, D.H.: Selective Cache Ways: On-Demand Cache Resource Allocation. In: Proc. International Symposium on Microarchitecture, pp. 248–259 (1999)Google Scholar
  12. 12.
    Banerjee, S., Nandy, G.S., Program, S.K.: Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency. In: Proc. Asia and South Pacific Design Automation Conference (ASPDAC), pp. 884–889 (2007)Google Scholar
  13. 13.
    Buyuktosunoglu, A., et al.: A Circuit-Level Implementation of an Adaptive-Issue Queue for Power-Aware Microprocessors. In: Proc. Great Lakes Symp. VLSI, pp. 73–78. ACM Press, New York (2001)Google Scholar
  14. 14.
    Nacul, A., Givargis, T.: Dynamic Voltage and Cache Reconfiguration for Low Power. In: Proc. Design Automation and Test in Europe (DATE), pp. 1376–1377 (2004)Google Scholar
  15. 15.
    Martello, S., Toth, P.: Knapsack problems: algorithms and computer implementations. Wiley, Chichester (1990)zbMATHGoogle Scholar
  16. 16.
    Liu, C.L., Layland, J.W.: Scheduling Algorithms for Multiprogramming in a Hard Real-Time Environment. Journal of the ACM 20(1), 40–61 (1973)CrossRefMathSciNetGoogle Scholar
  17. 17.
    Lehoczky, J.P., Sha, L., Ding, Y.: The Rate Monotonic Scheduling Algorithm: Exact Characterization and Average Case Behavior. In: Proc. IEEE Real Time Systems Symposium (RTSS), pp. 166–171 (1989)Google Scholar
  18. 18.
    SimpleScalar Tools,
  19. 19.
  20. 20.
    Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., Brown, R.B.: MiBench: A Free, Commercially Representative Embedded Benchmark Suite. In: IEEE Annual Workshop on Workload Characterization (2001)Google Scholar
  21. 21.
    Scott, J., Lee, L., Arends, J., Moyer, B.: Designing the Low-Power M*CORE Architecture. In: Proc. International Symposium on Computer Architecture Power Driven Microarchitecture Workshop, pp. 145–150 (1998)Google Scholar
  22. 22.
    Texas Instruments, Application Report, SPRA848A: Using the Power Scaling Library (2004)Google Scholar
  23. 23.
    Texas Instruments, Application Report, SPRAA19A: Power Management in an RF5 Audio Streaming Application Using DSP/BIOS (August 2005)Google Scholar
  24. 24.
    Lee, S., Sakurai, T.: Run-Time Voltage Hopping for Low-Power Real-Time Systems. In: Proc. Design Automation Conference (DAC), pp. 806–809 (2000)Google Scholar
  25. 25.
    Mochocki, B.C., Hu, X.S., Quan, G.: A Unified Approach to Variable Voltage Scheduling for Nonideal DVS Processors. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems 23(9), 1370–1377 (2004)CrossRefGoogle Scholar
  26. 26.
    Huang, M., Renau, J., Yoo, S.M., Torrellas, J.: A Framework for Dynamic Energy Efficiency and Temperature Management. In: Proc. International Symposium on Microarchitecture (MICRO), pp. 202–213 (2000)Google Scholar
  27. 27.

Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Gang Zeng
    • 1
  • Hiroyuki Tomiyama
    • 1
  • Hiroaki Takada
    • 1
  1. 1.Graduate School of Information Science, Nagoya University, Furo-cho, Chikusa-ku, Nagoya 464-8603Japan

Personalised recommendations