Abstract
RF-powered smart cards are widely used in different application areas today. The complexity and functionality of smart cards is growing continuously. This results in a higher power consumption. The power consumed is heavily depending on the software executed on the system. The power profile, especially the power peaks, of an executed application influence the system stability. If the power consumed by such a device exceeds the power provided by the RF-field a reset can be triggered by the power control unit or otherwise the chip may stay in an unpredictable state. Flattening the power profile can thus increase the stability of a system.
We present an optimization system which intends to eliminate critical peaks after the analysis of the power profile of an executed application. In an iterative compile process an optimal tradeoff between power and performance has to be found. This is achieved by selecting or deselecting different optimization passes on the intermediate language level of the compiler.
Chapter PDF
Similar content being viewed by others
Keywords
References
Haid, J., Kargl, W., Leutgeb, T., Scheiblhofer, D.: Power Management for RF-Powered vs. Battery-Powered Devices. In: Proceedings of Workshop on Wearable and Pervasive Computing, Graz, Austria (2005)
Rothbart, K., Neffe, U., Steger, C., Weiss, R., Rieger, E., Muehlberger, A.: Power consumption profile analysis for security attack simulation in smart cards at high abstraction level. In: EMSOFT 2005. Proceedings of the 5th ACM international conference on Embedded software, Jersey City, NJ, USA, pp. 214–217. ACM Press, New York (2005)
Tiwari, V., Malik, S., Wolfe, A.: Power analysis of embedded software: a first step towards software power minimization. In: ICCAD 1994. Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, IEEE Computer Society Press, Los Alamitos (1994)
Tiwari, V., Malik, S., Wolfe, A., Lee, M.T.C.: Instruction level power analysis and optimization of software. J. VLSI Signal Process. Syst. 13(2-3), 223–238 (1996)
Knijnenburg, P.M.W., Kisuki, T., O’Boyle, M.F.P.: Iterative compilation, 171–187 (2002)
Kisuki, T., Knijnenburg, P.M.W., O’Boyle, M.F.P.: Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation. In: PACT 2000. Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques, Washington, DC, USA, p. 237. IEEE Computer Society, Los Alamitos (2000)
Fursin, G., O’Boyle, M., Knijnenburg, P.: Evaluating Iterative Compilation, 305–315 (2002)
Cooper, K.D., Grosul, A., Harvey, T.J., Reeves, S., Subramanian, D., Torczon, L., Waterman, T.: ACME: adaptive compilation made efficient. In: LCTES 2005. Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, Chicago, Illinois, USA, pp. 69–77. ACM Press, New York (2005)
Cooper, K.D., Schielke, P.J., Subramanian, D.: Optimizing for reduced code space using genetic algorithms. In: LCTES 1999. Proceedings of the ACM SIGPLAN 1999 workshop on Languages, compilers, and tools for embedded systems, Atlanta, Georgia, United States, pp. 1–9. ACM Press, New York (1999)
Cooper, K.D., Subramanian, D., Torczon, L.: Adaptive Optimizing Compilers for the 21st Century. J. Supercomput. 23(1), 7–22 (2002)
Kulkarni, P., Zhao, W., Moon, H., Cho, K., Whalley, D., Davidson, J., Bailey, M., Paek, Y., Gallivan, K.: Finding effective optimization phase sequences. SIGPLAN Not. 38(7), 12–23 (2003)
Fursin, G., Cohen, A.: Building a Practical Iterative Interactive Compiler. In: De Bosschere, K., Kaeli, D., Stenström, P., Whalley, D., Ungerer, T. (eds.) HiPEAC 2007. LNCS, vol. 4367, Springer, Heidelberg (2007)
Gheorghita, S., Corporaal, H., Basten, T.: Using Iterative Compilation to Reduce Energy Consumption. In: ASCI 2004. Proceedings of the 10th Annual Conference of the Advanced School for Computing and Imaging, Delft, The Netherlands, pp. 197–202 (2004)
Neffe, U., Rothbart, K., Steger, C., Weiss, R., Rieger, E., Muehlberger, A.: A Flexible and Accurate Model of an Instruction-Set Simulator for Secure Smart Card Software Design. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds.) PATMOS 2004. LNCS, vol. 3254, pp. 491–500. Springer, Heidelberg (2004)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Grumer, M. et al. (2007). Software Power Peak Reduction on Smart Card Systems Based on Iterative Compiling. In: Denko, M.K., et al. Emerging Directions in Embedded and Ubiquitous Computing. EUC 2007. Lecture Notes in Computer Science, vol 4809. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-77090-9_58
Download citation
DOI: https://doi.org/10.1007/978-3-540-77090-9_58
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-77089-3
Online ISBN: 978-3-540-77090-9
eBook Packages: Computer ScienceComputer Science (R0)