Neuromorphic Adaptable Ocular Dominance Maps

  • Priti Gupta
  • Mukti Bansal
  • C. M. Markan
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4815)


Time staggered winner-take-all (ts-WTA) is a novel analog CMOS neuron cell [8], that computes ‘sum of weighted inputs” implemented as floating gate pFET ‘synapses’. The cell behavior exhibits competitive learning (WTA) so as to refine its weights in response to stimulation by input patterns staggered over time such that at the end of learning, the cell’s response favors one input pattern over others to exhibit feature selectivity. In this paper we study the applicability of this cell to form feature specific clusters and show how an array of these cells when connected through an RC-network, interacts diffusively so as to form clusters similar to those observed in cortical ocular dominance maps. Adaptive feature maps is a mechanism by which nature optimize its resources so as to have greater acuity for more abundant features. Neuromorphic feature maps can help design generic machines that can emulate this adaptive behavior.


Floating Gate pFET competitive learning WTA Feature maps ocular dominance 


  1. 1.
    Horng, S.H., Sur, M.: Visual activity and cortical rewiring: activity-dependent plasticity of cortical networks. Progress in Brain Research 157, 3–11 (2006)CrossRefGoogle Scholar
  2. 2.
    Choi, T.Y.W., et al.: Neuromorphic Implementation of Orientation Hypercolumns. IEEE Tran. on Circuit & Systems-I 52(6), 1049–1060 (2005)CrossRefGoogle Scholar
  3. 3.
    Merabet, L.B., et al.: What blindness can tell us about seeing again: merging neuroplasticity and neuroprostheses. Nature Reviews Neurosci. 6, 71–77 (2005)CrossRefGoogle Scholar
  4. 4.
    Diorio, C., Hasler, P., Minch, B.A., Mead, C.A.: A Single-Transistor Silicon Synapse. IEEE Transactions on Electron Devices 43(11), 1972–1980 (1996)CrossRefGoogle Scholar
  5. 5.
    Hsu, D., Figueroa, M., Diorio, C.: Competitive learning with floating-gate circuits. IEEE Transactions on Neural Networks 13(3), 732–744 (2002)CrossRefGoogle Scholar
  6. 6.
    Rahimi, K., Diorio, C., Hernandez, C., Brockhausen, M.D.: A simulation model for floating gate MOS synapse transistors. In: ISCAS (2002)Google Scholar
  7. 7.
    Grossberg, S.: Adaptive pattern classification and universal recoding: I. Parallel development and coding of neural feature detectors. Biol. Cybern. 23, 121–134 (1988)CrossRefMathSciNetGoogle Scholar
  8. 8.
    Bansal, M., Markan, C.M.: Floating gate Time staggered WTA for feature selectivity. In: Proc. of Workshop on Self-organizing Maps, WSOM 2003, Kitakyushu, Japan (2003)Google Scholar
  9. 9.
    Lazzaro, J., Ryckbusch, S., Mahowald, M.A., Mead, C.A.: Winner-take-all Networks of O(N) complexity, NIPS 1 Morgan Kaufman Publishers, San Mateo, CA, pp. 703–711 (1989) Google Scholar
  10. 10.
    Kruger, W., Hasler, P., Minch, B., Koch, C.: An adaptive WTA using floating gate technology. In: Advances in NIPS 9, pp. 713–719. MIT Press, Cambridge (1997)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Priti Gupta
    • 1
  • Mukti Bansal
    • 1
  • C. M. Markan
    • 1
  1. 1.VLSI Design Technology Lab, Department of Physics & Computer Science, Dayalbagh Educational Institute, AGRA – 282005 

Personalised recommendations