Abstract
Several logic styles such as Masked Dual-Rail Pre-charge Logic (MDPL) and Dual-Rail Random Switching Logic (DRSL) have been recently proposed to make implementations resistant against power analysis attacks. In this paper, it is shown that the circuits which contain sequential elements, flip-flops, and implemented in MDPL or DRSL styles are vulnerable to DPA attacks. Based on our results, the information leakage of CMOS D-flip-flops that are used to construct MDPL and DRSL D-flip-flops is the cause of this vulnerability. To reduce the leakage, a modification on the structure of the MDPL and DRSL flip-flops are proposed; two CMOS D-flip-flops are used in the suggested structure. The proposed technique shows a significant reduction in the information leakage of MDPL and DRSL flip-flops.
This project is partially supported by Iran National Science Foundation and Iran Telecommunication Research Center.
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Moradi, A., Salmasizadeh, M., Shalmani, M.T.M. (2007). Power Analysis Attacks on MDPL and DRSL Implementations. In: Nam, KH., Rhee, G. (eds) Information Security and Cryptology - ICISC 2007. ICISC 2007. Lecture Notes in Computer Science, vol 4817. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-76788-6_21
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DOI: https://doi.org/10.1007/978-3-540-76788-6_21
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