Abstract
A typical design exploration process using simulation tools for various cache parameters is a rather time-consuming process, even for low complexity applications. The main goal of an estimation methodology, introduced in this paper, is to provide fast and accurate estimates of the instruction cache miss rate of data-intensive applications implemented on a programmable embedded platform with multi-level instruction cache memory hierarchy, during the early design phases. Information is extracted from both the high-level code description (C code) of the application and its corresponding assembly code, without carrying out any kind of simulation. The proposed methodology requires only a single execution of the application in a general-purpose processor and uses only the assembly code of the targeted embedded processor. In order to automate the estimation procedure, a novel software tool named m-FICA implements the proposed methodology. The miss rate of two-level instruction cache can be estimated with high accuracy (>95%), comparing with simulation-based results while the required time cost is much smaller (orders of magnitude) than the simulation-based approaches.
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Kroupis, N., Soudris, D. (2007). Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate. In: Azémard, N., Svensson, L. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2007. Lecture Notes in Computer Science, vol 4644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74442-9_49
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DOI: https://doi.org/10.1007/978-3-540-74442-9_49
Publisher Name: Springer, Berlin, Heidelberg
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