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Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 4644))

Abstract

We present an accurate RT level estimation methodology describing the power consumption of a component under power gating. By developing separate models for the on- and off-state and the transition cost between them, we can limit errors to below 10% compared to SPICE. The models support several implementation styles of power gating as NMOS/PMOS or Super-Cutoff. Additionally the models can be used to size the sleep transistors more accurate. We show, how the models can be integrated into a high level power estimation framework supporting design space exploration for several design for leakage methodologies.

This work was supported by the European Commission within the Sixth Framework Programme through the MAP2 project (contract no. FP6-2004-SME-COOP MAP2-031984).

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Nadine Azémard Lars Svensson

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© 2007 Springer-Verlag Berlin Heidelberg

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Rosinger, S., Helms, D., Nebel, W. (2007). RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating . In: Azémard, N., Svensson, L. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2007. Lecture Notes in Computer Science, vol 4644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74442-9_27

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  • DOI: https://doi.org/10.1007/978-3-540-74442-9_27

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-74441-2

  • Online ISBN: 978-3-540-74442-9

  • eBook Packages: Computer ScienceComputer Science (R0)

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