Abstract
We present an accurate RT level estimation methodology describing the power consumption of a component under power gating. By developing separate models for the on- and off-state and the transition cost between them, we can limit errors to below 10% compared to SPICE. The models support several implementation styles of power gating as NMOS/PMOS or Super-Cutoff. Additionally the models can be used to size the sleep transistors more accurate. We show, how the models can be integrated into a high level power estimation framework supporting design space exploration for several design for leakage methodologies.
This work was supported by the European Commission within the Sixth Framework Programme through the MAP2 project (contract no. FP6-2004-SME-COOP MAP2-031984).
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Benini, L., De Micheli, G.: Dynamic Power Management. In: Design Techniques and CAD Tools, Kluwer Academic Publishers, Dordrecht (1998)
Pedram, M., Rabaey, J.: Power Aware Design Methodologies. Kluwer Academic Publishers, Dordrecht (2002)
Min, K.-S., Sakurai, T.: Zigzag Super Cut-off CMOS (ZSCCMOS) Scheme with Self-Saturated Virtual Power Lines for Subthreshold-Leakage-Suppressed Sub-1V-VDD LSI’s. In: Proceedings of the 28th European Solid-State Circuits Conference, 2002, pp. 679–682 (2002)
Jiang, H., Marek-Sadowska, M., Nassif, S.R.: Benefits and Costs of Power-Gating Technique. In: Proceedings of the 2005 International Conference on Computer Design, 2005, pp. 559–566 (2005)
Kao, J., Chandrakasan, A., Antoniadis, D.: Transistor sizing issues and tool for multithreshold CMOS technology. In: Proceedings 34th Design Automation Conference, June 1997, pp. 409–414 (1997)
Ramalingam, A., Zhang, B., Devgan, A., Pan, D.Z.: Sleep transistor sizing using timing criticality and temporal currents. In: Proceedings of the 2005 conference on Asia South Pacific design automation, 2005, pp. 1094–1097 (2005)
Hu, Z., Buyuktosunoglu, A., Srinivasan, V., Zyuban, V., Jacobson, H., Bose, P.: Microarchitectural techniques for power gating of execution units. In: ISLPED 2004: Proceedings of the 2004 international symposium on Low power electronics and design (2004)
Kawaguchi, H., Nose, K., Sakurai, T.: A super cut-off CMOS(SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current. IEEE Journal of Solid-State Circuits 35, 1498–1501 (2000)
Kruse, L.: Estimating and Optimizing Power Consumption of Integrated Macro Blocks at the Behavioral Level, Dissertation (2001)
Hoyer, M., Helms, D., Nebel, W.: Modeling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components. In: PATMOS, LNCS, Springer, Heidleberg (2007)
Helms, D., Hoyer, M., Nebel, W.: Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-junction Leakage. In: Vounckx, J., Azemard, N., Maurine, P. (eds.) PATMOS 2006. LNCS, vol. 4148, pp. 56–65. Springer, Heidelberg (2006)
Kanzow, C., Yamashita, N., Fukushima, M.: Levenberg-Marquardt methods for constrained nonlinear equations with strong local convergence properties. Journal of Computational and Applied Mathematics 172, 375–397 (2004)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Rosinger, S., Helms, D., Nebel, W. (2007). RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating . In: Azémard, N., Svensson, L. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2007. Lecture Notes in Computer Science, vol 4644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74442-9_27
Download citation
DOI: https://doi.org/10.1007/978-3-540-74442-9_27
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-74441-2
Online ISBN: 978-3-540-74442-9
eBook Packages: Computer ScienceComputer Science (R0)