Abstract
A novel algorithm for field programmable gate array (FPGA) realization of kNN classifier is presented in this paper. The algorithm identifies first k closest vectors in the design set of a kNN classifier for each input vector by performing the partial distance search (PDS) in the wavelet domain. It employs subspace search, bitplane reduction and multiple-coefficient accumulation techniques for the effective reduction of the area complexity and computation latency. The proposed implementation has been embedded in a softcore CPU for physical performance measurement. Experimental results show that the implementation provides a cost-effective solution to the FPGA realization of kNN classification systems where both high throughput and low area cost are desired.
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Yeh, YJ., Li, HY., Hwang, WJ., Fang, CY. (2007). FPGA Implementation of kNN Classifier Based on Wavelet Transform and Partial Distance Search. In: Ersbøll, B.K., Pedersen, K.S. (eds) Image Analysis. SCIA 2007. Lecture Notes in Computer Science, vol 4522. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-73040-8_52
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DOI: https://doi.org/10.1007/978-3-540-73040-8_52
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-73039-2
Online ISBN: 978-3-540-73040-8
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