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Bounded Model Checking Combining Symbolic Trajectory Evaluation Abstraction with Hybrid Three-Valued SAT Solving

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Part of the book series: Lecture Notes in Computer Science ((LNISA,volume 4402))

Abstract

Bounded Model Checking (BMC) based on SAT is a complementary technique to BDD-based Symbolic Model Checking, and it is useful for finding counterexamples of minimum length. However, for model checking of large real world systems, BMC is still limited by the state explosion problem, thus abstraction is essential. In this paper, BMC is implemented on a higher abstraction level – Register Transfer Level (RTL) within an abstraction framework of symbolic trajectory evaluation and hybrid three-valued SAT solving. An efficient SAT solver for RTL circuits is presented, and it is modified into a three-valued solver for the cooperative BMC application. The experimental results comparing with the ordinary BMC without abstraction show the efficiency of our method.

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References

  1. Moskewicz, M.W., et al.: Chaff: Engineering an efficient sat solver. In: Proc. of Design Automation Conference (DAC 2001), Las Vegas, NV, USA, pp. 530–535 (2001)

    Google Scholar 

  2. Prasad, M.R., Biere, A., Gupta, A.: A survey of recent advances in sat-based formal verification. Journal on STTT 7(2), 156–173 (2005)

    Article  Google Scholar 

  3. Biere, A., et al.: Symbolic model checking using sat procedures instead of bdds. In: Proc. of the 36th Design Automation Conference (DAC 1999), New Orleans, LA, USA, pp. 317–320 (1999)

    Google Scholar 

  4. Biere, A., et al.: Bounded model checking. Advances in Computers 58 (2003)

    Google Scholar 

  5. Clarke, E.M., Grumberg, O., Peled, D.A.: Model Checking. The MIT Press, Cambridge (1999)

    Google Scholar 

  6. Kang, H.J., Park, I.C.: SAT-based unbounded symbolic model checking. IEEE Trans. on CAD of Integrated Circuits and Systems 24(2), 129–140 (2005)

    Article  Google Scholar 

  7. Seger, C.-J.H., Bryant, R.E.: Formal verification by symbolic evaluation of partially-ordered trajectories. Formal methods in System Design 6(2), 147–190 (1995)

    Article  Google Scholar 

  8. Roorda, J.W., Claessen, K.: A new sat-based algorithm for symbolic trajectory evaluation. In: Borrione, D., Paul, W. (eds.) CHARME 2005. LNCS, vol. 3725, pp. 238–253. Springer, Heidelberg (2005)

    Chapter  Google Scholar 

  9. Roorda, J.W.: Symbolic trajectory evaluation using a satisfiability solver. Licentiate thesis, Chalmers University of Technology (2005)

    Google Scholar 

  10. Bjesse, P., Mokkedem, A., Leonard, T.: Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers. In: Berry, G., Comon, H., Finkel, A. (eds.) CAV 2001. LNCS, vol. 2102, pp. 454–464. Springer, Heidelberg (2001)

    Google Scholar 

  11. Yang, J., Singerman, E.: satgste: Combining the abstraction of gste with the capacity of a sat solver. In: Proc. Designing Correct Circuits (DCC), Barcelona (2004)

    Google Scholar 

  12. Yang, J., Seger, C.J.H.: Introduction to generalized symbolic trajectory evaluation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11(3), 345–353 (2003)

    Article  Google Scholar 

  13. Davis, M., Logemann, G., Loveland, D.W.: A machine program for theorem-proving. Communications of the ACM 5(7), 394–397 (1962)

    Article  MATH  MathSciNet  Google Scholar 

  14. Parthasarathy, G., et al.: An efficient finite-domain constraint solver for circuits. In: Proc. of the 41th Design Automation Conference (DAC), pp. 212–217 (2004)

    Google Scholar 

  15. Brglez, F., Bryan, D., Koiminski, K.: Combinational profiles of sequential benchmark circuits. In: Proc. International Symposium on Circuits and Systems (ISCAS), pp. 1929–1934 (1989)

    Google Scholar 

  16. UCSB RTL Satisfiability by Constraint Solving - HDPLL (2005), http://cadlab.ece.ucsb.edu/downloads/HDPLL.html

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Weiming Shen Junzhou Luo Zongkai Lin Jean-Paul A. Barthès Qi Hao

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© 2007 Springer-Verlag Berlin Heidelberg

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Deng, S., Wu, W., Bian, J. (2007). Bounded Model Checking Combining Symbolic Trajectory Evaluation Abstraction with Hybrid Three-Valued SAT Solving. In: Shen, W., Luo, J., Lin, Z., Barthès, JP.A., Hao, Q. (eds) Computer Supported Cooperative Work in Design III. CSCWD 2006. Lecture Notes in Computer Science, vol 4402. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-72863-4_31

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  • DOI: https://doi.org/10.1007/978-3-540-72863-4_31

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-72862-7

  • Online ISBN: 978-3-540-72863-4

  • eBook Packages: Computer ScienceComputer Science (R0)

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