FPGA Implementation of Evolvable Characters Recognizer with Self-adaptive Mutation Rates

  • Jin Wang
  • Chang Hao Piao
  • Chong Ho Lee
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4431)

Abstract

As an alternative to traditional artificial neural network approaches to pattern recognition, a hardware-implemented evolvable characters recognizer is presented in this paper. The main feature of the proposed evolvable system is that all the components including the evolutionary algorithm (EA), fitness calculation, and virtual reconfigurable circuit are implemented in a Xilinx Virtex xcv2000E FPGA. This allows for a completely pipelined hardware implementation and yields a significant speedup in the system evolution. In order to optimize the performance of the evolutionary algorithm and release the users from the time-consuming process of mutation parameters tuning, a self-adaptive mutation rate control scheme is also introduced. An analysis of experimental results demonstrates that the proposed evolvable system using self-adaptive mutation rates is superior to traditional fixed mutation rate-based approaches.

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Copyright information

© Springer Berlin Heidelberg 2007

Authors and Affiliations

  • Jin Wang
    • 1
  • Chang Hao Piao
    • 2
  • Chong Ho Lee
    • 1
  1. 1.Department of Information & Communication Engineering, Inha University, IncheonKorea
  2. 2.Department of Automation Engineering, ChongQing University of Posts and Telecommunications, ChongqingChina

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