FPGA Implementation of Evolvable Characters Recognizer with Self-adaptive Mutation Rates

  • Jin Wang
  • Chang Hao Piao
  • Chong Ho Lee
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4431)


As an alternative to traditional artificial neural network approaches to pattern recognition, a hardware-implemented evolvable characters recognizer is presented in this paper. The main feature of the proposed evolvable system is that all the components including the evolutionary algorithm (EA), fitness calculation, and virtual reconfigurable circuit are implemented in a Xilinx Virtex xcv2000E FPGA. This allows for a completely pipelined hardware implementation and yields a significant speedup in the system evolution. In order to optimize the performance of the evolutionary algorithm and release the users from the time-consuming process of mutation parameters tuning, a self-adaptive mutation rate control scheme is also introduced. An analysis of experimental results demonstrates that the proposed evolvable system using self-adaptive mutation rates is superior to traditional fixed mutation rate-based approaches.


Mutation Rate FPGA Implementation Evolvable Hardware Pattern Recognition System Cartesian Genetic Programming 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Yao, X., Higuchi, T.: Promises and Challenges of Evolvable Hardware. IEEE Transactions on Systems, Man, and Cybernetics-Part C: Applications and Reviews 29(1), 87–97 (1999)CrossRefGoogle Scholar
  2. 2.
    Iwata, M., et al.: A Pattern Recognition System Using Evolvable Hardware. In: Ebeling, W., Rechenberg, I., Voigt, H.-M., Schwefel, H.-P. (eds.) PPSN 1996. LNCS, vol. 1141, pp. 761–770. Springer, Heidelberg (1996)CrossRefGoogle Scholar
  3. 3.
    Torresen, J.: A scalable approach to evolvable hardware. Journal of Genetic Programming and Evolvable Machines 3(3), 259–282 (2002)zbMATHCrossRefGoogle Scholar
  4. 4.
    Torresen, J., Bakke, J.W., Sekanina, L.: Recognizing Speed Limit Sign Numbers by Evolvable Hardware. In: Yao, X., Burke, E.K., Lozano, J.A., Smith, J., Merelo-Guervós, J.J., Bullinaria, J.A., Rowe, J.E., Tiňo, P., Kabán, A., Schwefel, H.-P. (eds.) PPSN 2004. LNCS, vol. 3242, pp. 682–691. Springer, Heidelberg (2004)Google Scholar
  5. 5.
    Zhang, Y., et al.: Digital Circuit Design Using Intrinsic Evolvable Hardware. In: Proc. of the 2004 NASA/DoD Conference on the evolvable Hardware, pp. 55–63. IEEE Computer Society Press, Los Alamitos (2004)CrossRefGoogle Scholar
  6. 6.
    Martínek, T., Sekanina, L.: An Evolvable Image Filter: Experimental Evaluation of a Complete Hardware Implementation in FPGA. In: Moreno, J.M., Madrenas, J., Cosp, J. (eds.) ICES 2005. LNCS, vol. 3637, pp. 76–85. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  7. 7.
    Wang, J., et al.: Using Reconfigurable Architecture-Based Intrinsic Incremental Evolution to Evolve a Character Classification System. In: Hao, Y., Liu, J., Wang, Y.-P., Cheung, Y.-m., Yin, H., Jiao, L., Ma, J., Jiao, Y.-C. (eds.) CIS 2005. LNCS (LNAI), vol. 3801, pp. 216–223. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  8. 8.
    Wang, J., Lee, C.H.: Introducing Partitioning Training Set Strategy to Intrinsic Incremental Evolution. In: Gelbukh, A., Reyes-Garcia, C.A. (eds.) MICAI 2006. LNCS (LNAI), vol. 4293, pp. 272–282. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  9. 9.
    Celoxica Inc., RC1000 Hardware Reference Manual V2.3 (2001)Google Scholar
  10. 10.
    Miller, J.F., Thomson, P.: Cartesian Genetic Programming. In: Poli, R., Banzhaf, W., Langdon, W.B., Miller, J., Nordin, P., Fogarty, T.C. (eds.) EuroGP 2000. LNCS, vol. 1802, pp. 121–132. Springer, Heidelberg (2000)Google Scholar
  11. 11.
    Sekanina, L.: Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware. In: Tyrrell, A.M., Haddow, P.C., Torresen, J. (eds.) ICES 2003. LNCS, vol. 2606, pp. 186–197. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  12. 12.
    Rogen, D., et al.: Parameter Control in Evolutionary Algorithm. IEEE Transactions on Evolutionary Computation 3(2), 124–141 (1999)CrossRefMathSciNetGoogle Scholar
  13. 13.
    Stomeo, E., et al.: Mutation Rate for Evolvable Hardware. Transactions on Engineering, Computing and Technology 7, 117–124 (2005)Google Scholar
  14. 14.
    Sekanina, L., Friedl, S.: On Routine Implementation of Virtual Evolvable Devices Using COMBO6. In: Proc. of the 2004 NASA/DoD Conference on Evolvable Hardware, pp. 63–70. IEEE Computer Society Press, Los Alamitos (2004)CrossRefGoogle Scholar
  15. 15.
    Kalganova, T.: Bidirectional Incremental Evolution in Extrinsic Evolvable Hardware. In: Proc. of the 2nd NASA/DoD Workshop on Evolvable Hardware, pp. 65–74. IEEE Computer Society Press, Los Alamitos (2000)CrossRefGoogle Scholar
  16. 16.
    Wolfram, S.: Universality and Complexity in Cellular Automata. Physica D 10, 1–35 (1984)CrossRefMathSciNetGoogle Scholar

Copyright information

© Springer Berlin Heidelberg 2007

Authors and Affiliations

  • Jin Wang
    • 1
  • Chang Hao Piao
    • 2
  • Chong Ho Lee
    • 1
  1. 1.Department of Information & Communication Engineering, Inha University, IncheonKorea
  2. 2.Department of Automation Engineering, ChongQing University of Posts and Telecommunications, ChongqingChina

Personalised recommendations