Design and Implementation of an Image CoProcessor

  • R. Ebrahimi Atani
  • S. Mirzakuchaki
  • S. Ebrahimi Atani
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5099)


This paper presents a novel DA based 2D DCT/DST coprocessor architecture for the synchronous design in a Xilinx FPGA device. A 1.2V, 90nm triple-oxide technology, Virtex-IV FPGA is used for final implementation and maximum operating frequency of 117 MHz is achieved. Using XPower toolbox, the total dynamic power consumption of 393 mW is measured. The paper presents the trade-offs involved in designing the architecture, and the design for performance issues.


Discrete Cosine Transform Digital Signal Processing Field Programmable Gate Array CORDIC Algorithm Distribute Arithmetic 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • R. Ebrahimi Atani
    • 1
  • S. Mirzakuchaki
    • 1
  • S. Ebrahimi Atani
    • 2
  1. 1.EE DepartmentIUST, NarmakTehranIran
  2. 2.Department of MathematicsGuilan University, Faculty of ScienceRashtIran

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