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Instruction Set Extension Generation with Considering Physical Constraints

  • I-Wei Wu
  • Shih-Chia Huang
  • Chung-Ping Chung
  • Jyh-Jiun Shann
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4367)

Abstract

In this paper, we propose new algorithms for both ISE exploration and selection with considering important physical constraints such as pipestage timing and instruction set architecture (ISA) format, silicon area and register file. To handle these considerations, an ISE exploration algorithm is proposed. It not only explores ISE candidates but also their implementation option to minimize the execution time meanwhile using less silicon area. In ISE selection, many researches only take silicon area into account, but it is not comprehensive. In this paper, we formulate ISE selection as a multiconstrained 0-1 knapsack problem so that it can consider multiple constraints. Results with MiBench indicate that under same number of ISE, our approach achieves 69.43%, 1.26% and 33.8% (max., min. and avg., respectively) of further reduction in silicon area and also has maximally 1.6% performance improvement compared with the previous one.

Keywords

Instruction set extension ASIP Extensible Processors Pipestage Timing Constraint 

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Copyright information

© Springer Berlin Heidelberg 2007

Authors and Affiliations

  • I-Wei Wu
    • 1
  • Shih-Chia Huang
    • 1
  • Chung-Ping Chung
    • 1
  • Jyh-Jiun Shann
    • 1
  1. 1.Dept. of Computer Science, National Chiao Tung University, HsinchuTaiwan

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