Toward an Automatic Code Layout Methodology

Abstract

This paper presents a study on an automatic code layout methodology for multi core architectures with explicit memory hierarchies. Code layout techniques are employed to run large programs on such systems. This study shows the effects of different buffer schemes and replacement policies on a set of benchmarks. These schemes are considered to be more flexible than current approaches. Moreover, these schemes can be used as a foundation to build frameworks for high level parallel programming models in such multi core architectures. The current work has been implemented in IBM’s Cell Broadband Engine, but it can be extended to similar architectures.