Abstract
Ladder Diagram (LD) is the most used programming language for Programmable Logical Controllers (PLCs). A PLC is a special purpose industrial computer used to automate industrial processes. Bugs in LD programs are very costly and sometimes are even a threat to human safety. We propose a model driven approach for formal verification of LD programs through model-checking. We provide a metamodel for a subset of the LD language. We define a time Petri net (TPN) semantics for LD programs through an ATL model transformation. Finally, we automatically generate behavioral properties over the LD models as LTL formulae which are then checked over the generated TPN using the model-checkers available in the Tina toolkit. We focus on race condition detection.
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
This work is supported by the topcased project, part of the french cluster Aerospace Valley (granted by the french DGE), cf. http://www.topcased.org
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Guasch, A., Quevedo, J., Milne, R.: Fault diagnosis for gas turbines based on the control system. Engineering Applications of Artificial Intelligence 13(4), 477–484 (2000)
International Electrotechnical Comission: IEC 61131-3 International Standard, Programmable Controllers, Part 3: Programming Languages (2003)
Tourlas, K.: An assessment of the IEC 1131 -3 standard on languages for programmable controllers. In: Daniel, P. (ed.) SAFECOMP 1997: the 16th International Conference on Computer Safety, Reliability and Security York, UK, September 7-10, 1997, pp. 210–219. Springer, Heidelberg (1997)
Schum, J.L.: Locksmithing and Electronic Security Wiring Diagrams. McGraw-Hill Professional, New York (2002)
Aiken, A., Fähndrich, M., Su, Z.: Detecting races in relay ladder logic programs. In: Steffen, B. (ed.) ETAPS 1998 and TACAS 1998. LNCS, vol. 1384, pp. 184–200. Springer, Heidelberg (1998)
Merlin, P., Farber, D.: Recoverability of communication protocols–implications of a theoretical study. Communications, IEEE Transactions on [legacy, pre - 1988] 24(9), 1036–1043 (1976)
Jouault, F., Kurtev, I.: Transforming Models with ATL. In: Bruel, J.-M. (ed.) MoDELS 2005. LNCS, vol. 3844, pp. 128–138. Springer, Heidelberg (2006)
Chaki, S., Clarke, E.M., Ouaknine, J., Sharygina, N., Sinha, N.: State/event-based software model checking. In: Boiten, E.A., Derrick, J., Smith, G.P. (eds.) IFM 2004. LNCS, vol. 2999, pp. 128–147. Springer, Heidelberg (2004)
Berthomieu, B., Ribet, P.O., Vernadat, F.: The tool TINA – construction of abstract state spaces for Petri nets and time Petri nets. International Journal of Production Research 42(14), 2741–2756 (2004)
Berthomieu, B., Vernadat, F.: Time petri nets analysis with tina. In: Third International Conference on Quantitative Evaluation of Systems, 2006. QEST 2006, pp. 123–124 (2006)
Berthomieu, B., Peres, F., Vernadat, F.: Model-checking bounded prioritrized time petri nets. In: Namjoshi, K.S., Yoneda, T., Higashino, T., Okamura, Y. (eds.) ATVA 2007. LNCS, vol. 4762, pp. 516–535. Springer, Heidelberg (2007)
Clarke, E.M., Biere, A., Raimi, R., Zhu, Y.: Bounded model checking using satisfiability solving. Formal Methods in System Design 19(1), 7–34 (2001)
Vernadat, F., Azéma, P., Michel, F.: Covering step graph. In: Billington, J., Reisig, W. (eds.) ICATPN 1996. LNCS, vol. 1091, pp. 516–535. Springer, Heidelberg (1996)
Godefroid, P.: Partial-Order Methods for the Verification of Concurrent Systems. LNCS, vol. 1032. Springer, Heidelberg (1996)
Jimenez, I., Lopez, E., Ramirez, A.: Synthesis of ladder diagrams from petri nets controller models. In: Proceedings of the 2001 IEEE International Symposium on Intelligent Control, 2001 (ISIC 2001), pp. 225–230 (2001)
Minas, M., Frey, G.: Visual plc-programming using signal interpreted petri nets. In: American Control Conference, 2002. Proceedings of the 2002, vol. 6, pp. 5019–5024 (2002)
Klein, S., Frey, G., Litz, L.: A petri net based approach to the development of correct logic controllers. In: Proceedings of the 2nd International Workshop on Integration of Specification Techniques for Applications in Engineering (INT 2002), Grenoble (France), pp. 116–129 (2002)
Frey, G.: Design and formal Analysis of Petri Net based Logic Control Algorithms (Dissertation, University of Kaiserslautern). Shaker Verlag, Aachen (2002)
Dierks, H.: PLC-automata: a new class of implementable real-time automata. Theoretical Computer Science 253(1), 61–93 (2001)
Heiner, M., Menzel, T.: Instruction list verification using a petri net semantics (1998)
Heiner, M., Menzel, T.: A petri net semantics for the plc language instruction list. In: IEE workshop on discrete event systems (1998)
Canet, G., Couffin, S., Lesage, J.J., Petit, A., Schnoebelen, P.: Towards the automatic verification of plc programs written in instruction list. In: 2000 IEEE International Conference on Systems, Man, and Cybernetics, vol. 4, pp. 2449–2454 (2000)
Moon, I.: Modeling programmable logic controllers for logic verification. Control Systems Magazine, IEEE 14(2), 53–59 (1994)
Rausch, M., Krogh, B.: Transformations between different model forms in discrete event systems. In: Computational Cybernetics and Simulation, 1997 IEEE International Conference on Systems, Man, and Cybernetics, 1997, October 12-15, 1997, vol. 3, pp. 2841–2846 (1997)
Bohumir Zoubek, J.M.R., Kwiatkowska, M.: Towards automatic verification of ladder logic programs. In: Proc. IMACS Multiconference on Computational Engineering in Systems Applications (CESA) (2003)
Huuck, R.: Software Verification for Programmable Logic Controllers. PhD thesis, Institute of Computer Science and Applied Mathematics, University of Kiel (2003)
Berthomieu, B., Farail, P., Gaufillet, P., Peres, F., Bodeveix, J.P., Filali, M., Saad, R., Vernadat, F., Garavel, H., Lang, F.: FIACRE: an intermediate language for model verification in the TOPCASED environment. In: European Congress on Embedded Real-Time Software (ERTS), Toulouse SEE (electronic medium) (2008), http://www.see.asso.fr
Vernadat, F., Percebois, C., Farail, P., Vingerhoeds, R., Rossignol, A., Talpin, J.P., Chemouil, D.: The TOPCASED Project - A Toolkit in OPen-source for Critical Applications and SystEm Development. In: Data Systems In Aerospace (DASIA), Berlin, Germany, 22/05/2006-25/05/2006, European Space Agency (ESA Publications) (2006), http://www.esa.int/publications (electronic medium)
Combemale, B., Crégut, X., Garoche, P.L., Thirioux, X., Vernadat, F.: A Property-Driven Approach to Formal Verification of Process Models. In: Cardoso, J., Cordeiro, J., Filipe, J., Pedrosa, V. (eds.) Enterprise Information System IX. Springer, Heidelberg (2008)
Nikora, A.P.: Developing formal correctness properties from natural language requirements. NASA: Jet Propulsion Laboratory (2006)
Jouault, F., Bézivin, J., Kurtev, I.: TCS: a DSL for the Specification of Textual Concrete Syntaxes in Model Engineering. In: 5th international conference on Generative Programming and Component Engineering (GPCE 2006) (October 2006)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2008 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Bender, D.F., Combemale, B., Crégut, X., Farines, J.M., Berthomieu, B., Vernadat, F. (2008). Ladder Metamodeling and PLC Program Validation through Time Petri Nets. In: Schieferdecker, I., Hartman, A. (eds) Model Driven Architecture – Foundations and Applications. ECMDA-FA 2008. Lecture Notes in Computer Science, vol 5095. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-69100-6_9
Download citation
DOI: https://doi.org/10.1007/978-3-540-69100-6_9
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-69095-5
Online ISBN: 978-3-540-69100-6
eBook Packages: Computer ScienceComputer Science (R0)