Security Evaluation of Asynchronous Circuits

  • Jacques J. A. Fournier
  • Simon Moore
  • Huiyun Li
  • Robert Mullins
  • George Taylor
Conference paper

DOI: 10.1007/978-3-540-45238-6_12

Part of the Lecture Notes in Computer Science book series (LNCS, volume 2779)
Cite this paper as:
Fournier J.J.A., Moore S., Li H., Mullins R., Taylor G. (2003) Security Evaluation of Asynchronous Circuits. In: Walter C.D., Koç Ç.K., Paar C. (eds) Cryptographic Hardware and Embedded Systems - CHES 2003. CHES 2003. Lecture Notes in Computer Science, vol 2779. Springer, Berlin, Heidelberg

Abstract

Balanced asynchronous circuits have been touted as a superior replacement for conventional synchronous circuits. To assess these claims, we have designed, manufactured and tested an experimental asynchronous smart-card style device. In this paper we describe the tests performed and show that asynchronous circuits can provide better tamper-resistance. However, we have also discovered weaknesses with our test chip, some of which have resulted in new designs, and others which are more fundamental to the asynchronous design approach. This has led us to investigate the novel approach of design-time security analysis rather than rely on post manufacture analysis.

Keywords

Asynchronous circuits Dual-Rail encoding Power Analysis EMA Fault Analysis Design-time security evaluation 

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Jacques J. A. Fournier
    • 1
  • Simon Moore
    • 2
  • Huiyun Li
    • 2
  • Robert Mullins
    • 2
  • George Taylor
    • 2
  1. 1.Security Technologies DepartmentGemplusLa CiotatFrance
  2. 2.Computer LaboratoryUniversity of CambridgeUSA

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