Abstract
This paper presents the design and implementation of a novel architecture for FIR filters on Xilinx Virtex FPGAs. The architecture is particularly useful for handling the problem of signal boundaries filtering, which occurs in finite length signal processing (e.g. image processing). It cleverly exploits the Shift Register Logic (SRL) component of the Virtex family in order to implement the necessary complex data scheduling, leading to considerable area savings compared to the conventional implementation (based on a hard router), with no speed penalty. Our architecture uses bit parallel arithmetic and is fully scalable and parameterisable. A case study based on the implementation of the standard low filter of the Daubechies-8 wavelet on Xilinx Virtex-E FPGAs is presented.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Proakis. J.G., Manolakis.D.G.: Introduction to Digital Signal Processing. McMillan Publishing, USA (1989)
Pirsch, P.: Architectures for Digital Signal Processing. John Wiley & Sons, Chichester (1999)
Vetterli, M., Kovacevic, M.: Wavelets and Subband Coding. Prentice Hall, New Jersey (1995)
Smith, M.J.T., Eddins, S.: Analysis/Synthesis techniques for subband image coding. IEEE Trans On Acoustics, Speech and Signal Processing, 1446–1456 (August 1990)
Chakrabarti, C.: A DWT based encoder architecture for symmetrically extended images. In: Proceedings of the International Symposium on Circuits and Systems (1999)
Benkrid, A., Benkrid, K., Crookes, D.: Design and Implementation of a Novel Architecture for Symmetric FIR filters with Boundary Handling on Xilinx Virtex FPGAs. In: IEEE Conference on Field-Programmable Technology (FPT 2002), December 16 (2002)
Parhi, K.K.: VLSI Digital Signal Processing Systems: Design and Implementation. John Wiley & Sons, Chichester (1999)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Benkrid, A., Benkrid, K., Crookes, D. (2003). Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_54
Download citation
DOI: https://doi.org/10.1007/978-3-540-45234-8_54
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-40822-2
Online ISBN: 978-3-540-45234-8
eBook Packages: Springer Book Archive