Abstract
In this paper, we propose a new mathematical DES description that allows us to achieve optimized implementations in term of ratio Throughput/Area. First, we get an unrolled DES implementation that works at data rates of 21.3 Gbps (333 MHz), using Virtex-II technology. In this design, the plaintext, the key and the mode (encryption/decrytion) can be changed on a cycle-by-cycle basis with no dead cycles. In addition, we also propose sequential DES and triple-DES designs that are currently the most efficient ones in term of resources used as well as in term of throughput. Based on our DES and triple-DES results, we also set up conclusions for optimized FPGA design choices and possible improvement of cipher implementations with a modified structure description.
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References
Rabaey, J.M.: Digital Integrated Circuits. Prentice Hall, Englewood Cliffs (1996)
Xilinx: Virtex 2.5V field programmable gate arrays data sheet, available from http://www.xilinx.com
Xilinx, Pasham, V., Trimberger, S.: High-Speed DES and Triple DES Encryptor/ Decryptor (August 2001), available from http://www.xilinx.com/xapp/xapp270.pdf
Schneier, B.: Applied Cryptography, 2nd edn. John Wiley & Sons, Inc., Chichester (1996)
National Bureau of Standards. FIPS PUB 46, The Data Encryption Standard. U.S. Departement of Commerce (January 1977)
Patterson, C.: High performance DES encryption in Virtex FPGAs using Jbits. In: Proc. of FCCM 2001, IEEE Computer Society, Los Alamitos (2000)
Trimberger, S., Pang, R., Singh, A.: A 12 Gbps DES encryptor/decryptor core in an FPGA. In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, vol. 1965, pp. 156–163. Springer, Heidelberg (2000)
Davio, M., Desmedt, Y., Fosséprez, M., Govaerts, R., Hulsbosch, J., Neutjens, P., Piret, P., Quisquater, J.J., Vandewalle, J., Wouters, P.: Analytical Characteristics of the DES. In: Chaum, D. (ed.) Advances in Cryptology - Crypto 1983, Berlin, pp. 171–202. Springer, Heidelberg (1983)
Helion Technology. High Performance DES and Triple-DES Core for XILINX FPGA, available from http://www.heliontech.com
CAST, Inc. Triple DES Encryption Core, available from http://www.cast-inc.com
CAST, Inc. DES Encryption Core, available from http://www.cast-inc.com
inSilicon. X–3 DES Triple DES Cryptoprocessor, available from http://www.insilicon.com
inSilicon. X DES Cryptoprocessor, available from http://www.insilicon.com
Chodowiec, P., Gaj, K., Bellows, P., Schott, B.: Experimental Testing of the Gigabit IPSec-Compliant Implementations of RIJNDAEL and Triple DES Using SLAAC-1V FPGA Accelerator Board. In: Davida, G.I., Frankel, Y. (eds.) ISC 2001. LNCS, vol. 2200, pp. 220–234. Springer, Heidelberg (2001)
Kaps, J.P., Paar, C.: Fast DES Implementations for FPGAs and Its Application to a Universal Key-Search Machine. In: Tavares, S., Meijer, H. (eds.) SAC 1998. LNCS, vol. 1556, pp. 234–247. Springer, Heidelberg (1999)
Rouvroy, G., Standaert, F., Quisquater, J., Legat, J.: Efficient Uses of FPGA’s for Implementations of DES and its Experimental Linear Cryptanalysis. Accepted for publication on April 2003 in IEEE Transactions on Computers, Special CHES Edition (2003)
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Rouvroy, G., Standaert, FX., Quisquater, JJ., Legat, JD. (2003). Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_19
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DOI: https://doi.org/10.1007/978-3-540-45234-8_19
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