Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models

  • Oliver Wahlen
  • Manuel Hohenauer
  • Gunnar Braun
  • Rainer Leupers
  • Gerd Ascheid
  • Heinrich Meyr
  • Xiaoning Nie
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2826)


This paper proposes a technique for extracting an instruction scheduler from a LISA processor description. The generated tool reads unscheduled, sequential assembly code from a C compiler. It schedules the instructions using an efficient backtracking scheduling algorithm that allows automated delay slot filling and utilization of instruction level parallelism. For an industrial network processor and a multimedia VLIW architecture the quality of the generated assembly code is compared to that of compilers with handwritten scheduler specifications.


Assembly Code List Scheduler Instruction Level Parallelism Architecture Exploration Instruction Latency 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Oliver Wahlen
    • 1
  • Manuel Hohenauer
    • 1
  • Gunnar Braun
    • 2
  • Rainer Leupers
    • 1
  • Gerd Ascheid
    • 1
  • Heinrich Meyr
    • 1
  • Xiaoning Nie
    • 3
  1. 1.Integrated Signal Processing SystemsAachen University of TechnologyAachenGermany
  2. 2.CoWare Inc.AachenGermany
  3. 3.Infineon TechnologiesMunichGermany

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