Abstract
The StrongARM processor features virtually-addressedcaches and a TLB without address-space tags. A naive implementation therefore requires flushing of all CPU caches and the TLB on each context switch, which is very costly. We present an implementation of fast context switches on the architecture in both Linux and the L4 microkernel. It is based on using domain tags as address-space identifiers and delaying cache flushes until a clash of mappings is detected. We observe a reduction of the context-switching overheads by about an order of magnitude compared to the naive scheme presently implemented in Linux.
We also implemented sharing of TLB entries for shared pages, a natural extension of the fast-context-switch approach. Even though the TLBs of the StrongARM are quite small and a potential bottleneck, we found that benefits from sharing TLB entries are generally marginal, and can only be expected to be significant under very restrictive conditions.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Liedtke, J., Elphinstone, K., Schönberg, S., Härtig, H., Heiser, G., Islam, N., Jaeger, T.: Achieved IPC performance (still the foundation for extensibility). In: Proceedings of the 6th Workshop on Hot Topics in Operating Systems (HotOS), Cape Cod, MA, USA, pp. 28–31 (1997)
Jagger, D. (ed.): Advanced RISC Machines Architecture Reference Manual. Prentice-Hall, Englewood Cliffs (1995)
ITRON Committee, TRON Association: μITRON4.0 Specification (1999), http://www.ertl.jp/ITRON/SPEC/mitron4-e.html
Liedtke, J.: On μ-kernel construction. In: Proceedings of the 15th ACM Symposium on OS Principles (SOSP), Copper Mountain, CO, USA, pp. 237–250 (1995)
Mery, D.: Symbian OSversion 7.0 functional description. White paper, Symbian Ltd. (2003), http://www.symbian.com/technology/whitepapers.html
Wiggins, A., Heiser, G.: Fast address-space switching on the StrongARM SA- 1100 processor. In: Proceedings of the 5th Australasian Computer Architecture Conference (ACAC), Canberra, Australia, pp. 97–104. IEEE CS Press, Los Alamitos (2000)
L4Ka Team: L4Ka — Pistachio kernel (2003), http://l4ka.org/projects/pistachio/
Chase, J.S., Levy, H.M., Feeley, M.J., Lazowska, E.D.: Sharing and protection in a single-address-space operating system. ACM Transactions on Computer Systems 12, 271–307 (1994)
Heiser, G., Elphinstone, K., Vochteloo, J., Russell, S., Liedtke, J.: The Mungi single-address-space operating system. Software: Practice and Experience 28, 901–928 (1998)
Intel Corp.: Intel StrongARM SA-1100 Microprocessor Developer’s Manual (1999)
Murray, J.: Inside Microsoft Windows CE. Microsoft Press (1998)
McVoy, L., Staelin, C.: lmbench: Portable tools for performance analysis. In: Proceedings of the 1996 USENIX Technical Conference, San Diego, CA, USA (1996)
Chapman, M., Wienand, I., Heiser, G.: Itanium page tables and TLB. Technical Report UNSW-CSE-TR-0307, School of Computer Science and Engineering, University of NSW, Sydney 2052, Australia (2003)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Wiggins, A., Tuch, H., Uhlig, V., Heiser, G. (2003). Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor. In: Omondi, A., Sedukhin, S. (eds) Advances in Computer Systems Architecture. ACSAC 2003. Lecture Notes in Computer Science, vol 2823. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39864-6_28
Download citation
DOI: https://doi.org/10.1007/978-3-540-39864-6_28
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20122-9
Online ISBN: 978-3-540-39864-6
eBook Packages: Springer Book Archive