Abstract
The outstanding forward error correction provided by Turbo-Codes made them part of today’s communications standards. Therefore, efficient Turbo-Decoder architectures are important building blocks in communications systems. In this paper we present a scalable, highly parallel architecture for UMTS compliant Turbo decoding and apply architecture-driven voltage scaling to reduce the energy consumption. We will show that this approach adds some additional, more energy-efficient solutions to the design space of Turbo decoding systems. It can save up to 34 % of the decoding energy per datablock, although the supply voltage can not arbitrarily selected. We present throughput, area, and estimated energy results for various degrees of parallelization based on synthesis on a 0.18 μm ASIC-technology library, which is characterized for two different supply voltages: nominal 1.8 V and nominal 1.3 V.
This work has been partially supported by the Deutsche Forschungsgemeinschaft (DFG) under Grant We 2442/1-2
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Gilbert, F., Wehn, N. (2003). Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_44
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DOI: https://doi.org/10.1007/978-3-540-39762-5_44
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