Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing
Positive Feedback Adiabatic Logic (PFAL) with minimal dimensioned transistors can save energy compared to static CMOS up to an operating frequency f = 200MHz. In this work the impact of transistor sizing is discussed, and design rules are analytically derived and confirmed by simulations. The increase of the p-channel transistor width can significantly reduce the resistance of the charging path decreasing the energy dissipation of the PFAL inverter by a factor of 2. In more complex gates a further design rule for the sizing of the n-channel transistors is proposed. Simulations of a PFAL 1-bit full adder show that the energy consumption can be reduced by additional 10% and energy savings can be achieved beyond f = 1GHz in a 0.13μm CMOS technology. The results are validated through the use of the design centering tool ‘WiCkeD’ .
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- 1.Antreich, K., Gräb, H., et al.: WiCkeD: Analog Circuit Synthesis Incorporating Mismatch. In: IEEE Custom Integrated Circuits Conference (CICC), Orlando, Florid (May 2000)Google Scholar
- 2.Amirante, E., Bargagli-Stoffi, A., Fischer, J., Iannaccone, G., Schmitt-Landsiedel, D.: Variations of the Power Dissipation in Adiabatic Logic Gates. In: Proceedings of the 11th International Workshop on Power And Timing Modeling, Optimization and Simulation, PATMOS 2001, Yverdon-les-Bains, Switzerland, September 2001, pp. 9.1.1–9.1.10 (2001)Google Scholar
- 4.Kramer, A., Denker, J.S., Flower, B., Moroney, J.: 2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits. In: Proceedings of the International Symposium on Low Power Design, pp. 191–196 (1995)Google Scholar
- 10.Weste, N.H.E., Eshraghian, K.: Principles of CMOS VLSI design: a systems perspective, 2nd edn. Addison-Wesley Publishing Company, Reading (1992)Google Scholar