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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2799))

Abstract

Power estimation at the Register-Transfer level is usually narrowed down to the problem of building accurate power models for the RTL (synthetic) operators. In this work we show that, when RTL power estimation is integrated into a realistic design flow, other types of primitives need to be accurately modeled. In particular, we show that most of the RTL functionality is realized by sparse logic elements.

We thus propose statistical power models for these primitives, that we have validated on a set of industrial benchmarks.

This work is supported, in part, by the EC under contract IST-2001-30125 ”POET”

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References

  1. Gajski, D.D., Dutt, N.D., Wu, A.C.-H., Lin, S.Y.-L.: High-Level Synthesis Introduction to Chip and System Design. Kluwer Academic Publishers, Dordrecht (1992)

    Google Scholar 

  2. Synopsys DesignCompiler, http://www.synopsys.com/products/logic/design_compiler.html

  3. BullDast PowerChecker, http://www.bulldast.com/powerchecker.html

  4. Synopsys VSS, http://www.synopsys.com/products/simulation/vss_cs.html

  5. ModelTechnology ModelSim, http://www.model.com/products/default.asp

  6. Cadence NS-SIM, http://www.cadence.com/datasheets/affirma_nc_sim.html

  7. Bogliolo, A., Colonescu, I., Corgnati, R., Macii, E., Poncino, M.: An RTL Power Estimation Tool with On-Line Model Building Capabilities. In: PATMOS 2001, Yverdonles- bains, Switzerland (September 2001)

    Google Scholar 

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© 2003 Springer-Verlag Berlin Heidelberg

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Bruno, M., Macii, A., Poncino, M. (2003). A Statistical Power Model for Non-synthetic RTL Operators. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_27

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  • DOI: https://doi.org/10.1007/978-3-540-39762-5_27

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-20074-1

  • Online ISBN: 978-3-540-39762-5

  • eBook Packages: Springer Book Archive

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