Abstract
In this paper an analytical model to estimate crosstalk noise on capacitively and inductively coupled on-chip buses is derived. The analytical nature of the model enables its usage in complex systems where high simulation speed is essential. The model also combines together properties such as inductive coupling, initial conditions, signal rise time, switching time and bit patterns that haven’t been included in a single analytical crosstalk model before. The model is compared to three previous crosstalk noise estimation models. The error of the model remains below four percent when compared to HSPICE. It is also demonstrated that for planar buses the five closest neighboring wires constitute up to 95% of the total induced crosstalk noise.
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References
Devgan, A.: Efficient Coupled Noise Estimation for On-Chip Interconnects. In: IEEE/ACM International Conference on Computer-Aided Design (1997)
Servel, G., Deschacht, D.: On-Chip Crosstalk Evaluation Between Adjacent Interconnections. In: IEEE International Conference on Electronics, Circuits and Systems (2000)
Kahng, A.B., Muddu, S., Pol, N., Vidhani, D.: Noise Model for Multiple Segmented Coupled RC Interconnects. In: International Symposium on Quality in Electronic Design (2001)
Kawaguchi, H., Sakurai, T.: Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines. In: Proceedings of Asia and South Pacific Design Automation Conference (1998)
Dhaou, I.B., Parhi, K., Tenhunen, H.: Energy Efficient Signaling in Deep Submicron CMOS Technology. Special Issue on Timing Analysis and Optimization for Deep Sub-Micron ICs, VLSI Design Journal (2002)
Chen, J., He, L.: A Decoupling Method for Analysis of Coupled RLC Interconnects. In: IEEE/ACM International Great Lakes Symposium on VLSI (2002)
Choi, S.H., Paul, B.C., Roy, K.: Dynamic Noise Analysis with Capacitive and Inductive Coupling. In: IEEE International Conference on VLSI Design (2002)
Becer, M., Hajj, I.N.: An Analytical Model for Delay and Crosstalk Estimation in Interconnects under General Switching Conditions. In: IEEE International Conference on Electronics, Circuits and Systems (2000)
Paul, C.: Analysis of Multiconductor Transmission Lines. John Wiley & Sons, Chichester (1994)
Granzow, K.D.: Digital Transmission Lines, Computer Modelling and Analysis. Oxford University Press, Oxford (1998)
Siebert, W.M.: Circuits, Signals and Systems. MIT Press, Cambridge (1986)
Tuuna, S.: Modelling and Analysis of Crosstalk on High-Performance On-Chip Buses. Master’s Thesis, University of Turku (2002)
Kahng, A.B., Muddu, S., Vidhani, D.: Noise and Delay Uncertainty Studies for Coupled RC Interconnects. In: IEEE International ASIC/SOC Conference (1999)
Djordjevic, A., Bazdar, M., Sarkar, T., Harrington, R.: LINPAR for Windows: Matrix Parameters for Multiconductor Transmission Lines, Software and User’s Manual, Version 2.0. Artech House Publishers (1999)
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Tuuna, S., Isoaho, J. (2003). Estimation of Crosstalk Noise for On-Chip Buses. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_13
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DOI: https://doi.org/10.1007/978-3-540-39762-5_13
Publisher Name: Springer, Berlin, Heidelberg
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