Abstract
A tool to model interconnect parasitics in radio-frequency (RF) integrated circuits (RFICs) is presented. Accurate modeling is achieved by combining a detailed RLC wire model together with a distributed RC substrate model. Wire geometry is fractured to ensure accurate modeling of wave propagation as well as displacement current due to substrate losses. The wire model includes resistance and coupled capacitance together with self and mutual inductance. The necessity of including a distributed RC model of the substrate is stressed. RLC reduction at the end of parasitic extraction allows for fast simulation of the complete model. Accuracy and performance are demonstrated by comparing the values extracted by the tool against results from existing computer software as well as against silicon measurements.
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Lescot, J., Clément, F.J.R. (2003). Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_12
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DOI: https://doi.org/10.1007/978-3-540-39762-5_12
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20074-1
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