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Kilo-instruction Processors

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Book cover High Performance Computing (ISHPC 2003)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2858))

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Abstract.

Due to the difference between processor speed and memory speed, the latter has steadily appeared further away in cycles to the processor. Superscalar out-of-order processors cope with these increasing latencies by having more in-flight instructions from where to extract ILP. With coming latencies of 500 cycles and more, this will eventually derive in what we have called Kilo-Instruction Processors, which will have to handle thousands of in-flight instructions. Managing such a big number of in-flight instructions must imply a microarchitectural change in the way the re-order buffer, the instructions queues and the physical registers are handled, since simply up-sizing these resources is technologically unfeasible. In this paper we present a survey of several techniques which try to solve these problems caused by thousands of in-flight instructions.

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Author information

Authors and Affiliations

  1. Departamento de Arquitectura de Computadores, Universidad Politécnica de Cataluña, Barcelona, Spain

    Adrián Cristal, Daniel Ortega, Josep Llosa & Mateo Valero

Authors
  1. Adrián Cristal
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  2. Daniel Ortega
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  3. Josep Llosa
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  4. Mateo Valero
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Editor information

Editors and Affiliations

  1. Department of Computer Science, University of California (UCI), 3019 Donald Bren Hall, 92697-3435, Irvine, CA, USA

    Alex Veidenbaum

  2. Department of Information and Computer Science, Faculty of Science, Nara women’s University, Kitauoyanishi-machi, Nara-city, 630-8506, Nara, Japan

    Kazuki Joe

  3. Keio University, Hiyoshi, Kohoku, Yokohama, 223–8522, Kanagawa, Japan

    Hideharu Amano

  4. Tokyo University of Technology, 1404-1 Katakura, Hachioji, 192-0982, Tokyo, Japan

    Hideo Aiso

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© 2003 Springer-Verlag Berlin Heidelberg

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Cristal, A., Ortega, D., Llosa, J., Valero, M. (2003). Kilo-instruction Processors. In: Veidenbaum, A., Joe, K., Amano, H., Aiso, H. (eds) High Performance Computing. ISHPC 2003. Lecture Notes in Computer Science, vol 2858. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39707-6_2

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  • DOI: https://doi.org/10.1007/978-3-540-39707-6_2

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-20359-9

  • Online ISBN: 978-3-540-39707-6

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