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Task Partitioning for Multi-core Network Processors

  • Robert Ennals
  • Richard Sharp
  • Alan Mycroft
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3443)

Abstract

Network processors (NPs) typically contain multiple concurrent processing cores. State-of-the-art programming techniques for NPs are invariably low-level, requiring programmers to partition code into concurrent tasks early in the design process. This results in programs that are hard to maintain and hard to port to alternative architectures. This paper presents a new approach in which a high-level program is separated from its partitioning into concurrent tasks. Designers write their programs in a high-level, domain-specific, architecturally-neutral language, but also provide a separate Architecture Mapping Script (AMS). An AMS specifies semantics-preserving transformations that are applied to the program to re-arrange it into a set of tasks appropriate for execution on a particular target architecture. We (i) describe three such transformations: pipeline introduction, pipeline elimination and queue multiplexing; and (ii) specify when each can be safely applied.

As a case study we describe an IP packet-forwarder and present an AMS script that partitions it into a form capable of running at 3Gb/s on an Intel IXP2400 Network Processor.

Keywords

Global Variable Concurrent Task Concurrent Program Source Program Target Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Robert Ennals
    • 1
  • Richard Sharp
    • 1
  • Alan Mycroft
    • 2
  1. 1.Intel Research CambridgeCambridgeUK
  2. 2.Computer LaboratoryCambridge UniversityCambridgeUK

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