Abstract
Statecharts is a visual formalism suitable for high-level system specification, while Verilog is a hardware description language that can be used for both behavioural and structural specification of (hardware) systems. This paper implements a semantics-preserving mapping from Graphical Statecharts to Verilog programs, which, to the best of our knowledge, is the first algorithm to bridge the gap between Statecharts and Verilog, and can be embedded into the hardware/software co-specification process [19] as a front-end.
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Tran, VA.V., Qin, S., Chin, W.N. (2005). An Automatic Mapping from Statecharts to Verilog. In: Liu, Z., Araki, K. (eds) Theoretical Aspects of Computing - ICTAC 2004. ICTAC 2004. Lecture Notes in Computer Science, vol 3407. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-31862-0_15
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DOI: https://doi.org/10.1007/978-3-540-31862-0_15
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