Verification of an Error Correcting Code by Abstract Interpretation

  • Charles Hymans
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3385)


We apply the theory of abstract interpretation to validate a Reed Solomon error correcting code. We design and implement an abstract simulator for VHDL descriptions. This tool computes an over-approximation of all the states that would be reached during any run of a conventional simulator. It collects linear constraints that hold between signals in the design. It is used to check the RTL implementations of the Reed Solomon encoder and decoder against correct high-level specifications. We explain how to express the correctness property so as to defeat the state explosion incurred by the deep pipeline in the decoder. Benchmarks show the abstract simulator is very frugal in both memory and time. Comparisons with VIS confirm that specialized tools outperform general purpose algorithms. Abstract simulation also competes advantageously with simulation. In less time than what was allocated for simulation by the designers of the components, it achieves full coverage.


Model Check Clock Cycle Error Correct Code Abstract Interpretation Abstract Domain 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Charles Hymans
    • 1
  1. 1.STIXÉcole PolytechniquePalaiseauFrance

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