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Combining Equivalence Verification and Completion Functions

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Part of the Lecture Notes in Computer Science book series (LNCS,volume 3312)


This work presents a new method for verifying optimized register-transfer-level implementations of pipelined circuits. We combine the robust, yet limited, capabilities of combinational equivalence verification with the modular and composable verification strategy of completion functions. We have applied this technique to a 32-bit OpenRISC processor and a Sobel edge-detector circuit. Each case study required less than fifteen verification obligations and each obligation could be checked in less than one minute. We believe that our approach will be applicable to a large class of pipelines with in-order execution.


  • Clock Cycle
  • Equivalence Checker
  • Pipeline Stage
  • Memory Array
  • Branch Instruction

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  • DOI: 10.1007/978-3-540-30494-4_8
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© 2004 Springer-Verlag Berlin Heidelberg

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Aagaard, M.D., Ciubotariu, V.C., Higgins, J.T., Khalvati, F. (2004). Combining Equivalence Verification and Completion Functions. In: Hu, A.J., Martin, A.K. (eds) Formal Methods in Computer-Aided Design. FMCAD 2004. Lecture Notes in Computer Science, vol 3312. Springer, Berlin, Heidelberg.

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-23738-9

  • Online ISBN: 978-3-540-30494-4

  • eBook Packages: Springer Book Archive