Abstract
The precise determination of worst-case execution times (WCETs) for programs is mostly being performed on fully linked executables, since all needed information is available and all machine parameters influencing cache performance are available to the analysis. This paper describes how to perform a component-wise prediction of the instruction cache behavior guaranteeing conservative results compared to an analysis of a fully linked executable. This proves the correctness of the method based on a previous proof of correctness of the analysis of fully linked executables. The analysis is described for a general A-way set associative cache. The only assumption is that the replacement strategy is LRU.
An extended abstract of this article has been accepted at the 4th Intl WORKSHOP ON WORST-CASE EXECUTION TIME (WCET) ANALYSIS, 2004.
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References
Cousot, P., Cousot, R.: Abstract interpretation frameworks. Journal of Logic and Computation 2(4), 511–547 (1992)
Ferdinand, C.: Cache Behavior Prediction for Real-Time Systems. PhD thesis, Saarland University (1997)
Ferdinand, C., Heckmann, R., Langenbach, M., Martin, F., Schmidt, M., Theiling, H., Thesing, S., Wilhelm, R.: Reliable and precise WCET determination for a real-life processor. In: Henzinger, T.A., Kirsch, C.M. (eds.) EMSOFT 2001. LNCS, vol. 2211, p. 469. Springer, Heidelberg (2001)
Levine, J.R.: Linkers And Loaders. Morgan Kaufmann Publishers, San Francisco (2000)
Martin, F.: PAG– an efficient program analyzer generator. International Journal on Software Tools for Technology Transfer 2(1) (1998)
Patil, K.S.: Compositional Static Cache Analysis Using Module-Level Abstraction. Master’s thesis, North Carolina State University (2003)
Renaux, D., Góes, J., Linhares, R.: WCET Estimation from Object Code implemented in the PERF Environment. In: 2nd International Workshop on Worst-Case Execution Time Analysis (Satellite Event to ECRTS 2002), Technical University of Vienna, Austria, June 18, pp. 28–35 (2002)
Min, S.L., et al.: AnAccurate Instruction Cache Analysis Technique for Real-time Systems. In: Proceedings of the Workshop on Architectures for Real-time Applications (April 1994)
Lim, S.-S., et al.: An Accurate Worst-Case Timing Analysis for RISC Processors. In: IEEE Real-Time Systems Symposium, pp. 97–108 (December 1994)
Theiling, H.: Extracting Safe and Precise Control Flow from Binaries. In: Proceedings of the 7th Conference on Real-Time Computing Systems and Applications, Cheju Island, South Korea (2000)
Wilhelm, R.: WhyAI + ILP is good forWCET, butMC is not, nor ILP alone. In: Proceedings of the Fifth International Conference on Verification, Model Checking and Abstract Interpretation, Venice, Italy (January 2004)
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Rakib, A., Parshin, O., Thesing, S., Wilhelm, R. (2004). Component-Wise Instruction-Cache Behavior Prediction. In: Wang, F. (eds) Automated Technology for Verification and Analysis. ATVA 2004. Lecture Notes in Computer Science, vol 3299. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30476-0_20
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DOI: https://doi.org/10.1007/978-3-540-30476-0_20
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23610-8
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