Parallel Performance of Hierarchical Multipole Algorithms for Inductance Extraction

Abstract

Parasitic extraction techniques are used to estimate signal delay in VLSI chips. Inductance extraction is a critical component of the parasitic extraction process in which on-chip inductive effects are estimated with high accuracy. In earlier work [1], we described a parallel software package for inductance extraction called ParIS, which uses a novel preconditioned iterative method to solve the dense, complex linear system of equations arising in these problems. The most computationally challenging task in ParIS involves computing dense matrix-vector products efficiently via hierarchical multipole-based approximation techniques. This paper presents a comparative study of two such techniques: a hierarchical algorithm called Hierarchical Multipole Method (HMM) and the well-known Fast Multipole Method (FMM). We investigate the performance of parallel MPI-based implementations of these algorithms on a Linux cluster. We analyze the impact of various algorithmic parameters and identify regimes where HMM is expected to outperform FMM on uniprocessor as well as multiprocessor platforms.

Support for Mahawar and Sarin was provided by NSF-CCR 9984400, NSF-CCR 0113668, and Texas ATP 000512-0266-2001 grants. Grama’s research was supported by NSF-EEC 0228390 and NSF-CCF 0325227 grants. Computational resources were acquired through NSF-DMS 0216275 grant.