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Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures

  • Nikhil Bansal
  • Sumit Gupta
  • Nikil Dutt
  • Alex Nicolau
  • Rajesh Gupta
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Abstract

Coarse-grain reconfigurable architectures consist of a large number of processing elements (PEs) connected together in a network. For mapping applications to such coarse-grain architectures, we present an algorithm that takes into account the number and delay of interconnects. This algorithm maps operations to PEs and data transfers to interconnects in the fabric. We explore three different cost functions that largely affect the performance of the scheduler: (a) priority of the operations, (b) affinity of operations to PEs based on past mapping decisions, and (c) connectivity between the PEs. Our results show that a priority-based operation cost function coupled with a connectivity-based PE cost function gives results that are close to the lower bounds for a range of designs.

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References

  1. 1.
    Hartenstein, R.W., Kress, R.: A datapath synthesis system for the reconfigurable datapath architecture. In: ASP-DAC (1995)Google Scholar
  2. 2.
    Ebeling, C., et al.: Mapping applications to the rapid configurable architectures. In: FCCM (1997)Google Scholar
  3. 3.
    Lee, W., et al.: Space-time scheduling of instruction-level parallelism on a RAWmachine. In: ASPLOS (1998)Google Scholar
  4. 4.
    Cadambi, S., Goldstein, S.C.: Fast and efficient place and route for pipeline reconfigurable architectures. In: ICCD (2000)Google Scholar
  5. 5.
    Singh, H., et al.: Morphosys: an integrated reconfigurable system for data parallel and computation-intensive applications. IEEE Transactions on Computers (2000)Google Scholar
  6. 6.
    Hartenstein, R.: A decade of reconfigurable computing:A visionary retrospective. In: DATE (2001)Google Scholar
  7. 7.
    Miyamori, T., Olukotun, K.: Remarc: Reconfigurable multimedia array coprocessor. In: FPGA (1998)Google Scholar
  8. 8.
    Becker, J., Glesner, M., Alsolaim, A., Starzyk, J.: Architecture and application of a dynamically reconfigurable hardware array for future mobile communication systems. In: FCCM (2000)Google Scholar
  9. 9.
    Schaumont, P., Verbauwhede, I., Sarrafzadeh, M., Keutzer, K.: A quick safari through the reconfigurable jungle. In: Design Automation Conference (2001)Google Scholar
  10. 10.
    Omitted for blind reviewGoogle Scholar
  11. 11.
    Omitted for blind reviewGoogle Scholar
  12. 12.
    Huang, Z., Malik, S.: Exploiting operational level parallelism through dynamically reconfigurable datapath. In: DAC (2002)Google Scholar
  13. 13.
    Callaham, T.J., Wawrzynek, J.: Adapting software pipelining for reconfigurable computing. In: CASES (2000)Google Scholar
  14. 14.
    Bondalapati, K., Prasanna, V.K.: Loop pipelining and optimization for run-time reconfiguration. In: RAW (2000)Google Scholar
  15. 15.
    Venkataramani, G., et al.: A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture. In: CASES (2001)Google Scholar
  16. 16.
    Lee, J., Choi, K., Dutt, N.: Compilation approach for coarse-grained reconfigurable architectures. IEEE D&T (2003)Google Scholar
  17. 17.
    Mei, B., et al.: Exploiting loop-level parallelism on coarse-grained reconfigurable architectures ucing modulo scheduling. In: DATE (2003)Google Scholar
  18. 18.
    Quinton, P., Robert, Y.: Systolic Algorithms and Architectures. Prentice-Hall, Englewood Cliffs (1991)Google Scholar
  19. 19.
    De Micheli, G.: Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York (1994)Google Scholar
  20. 20.
    Bittner, R.A., Athanas, P.M., Musgrove, M.D.: Colt: An experiment in wormhole run-time reconfiguration. SPIE, Bellingham (1996)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Nikhil Bansal
    • 1
  • Sumit Gupta
    • 2
  • Nikil Dutt
    • 1
  • Alex Nicolau
    • 1
  • Rajesh Gupta
    • 3
  1. 1.University of CaliforniaIrvine
  2. 2.Tallwood Venture CapitalPalo Alto
  3. 3.University of CaliforniaSan Diego

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