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Exploring Potential Benefits of 3D FPGA Integration

  • Cristinel Ababei
  • Pongstorn Maidee
  • Kia Bazargan
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Abstract

A new timing-driven partitioning-based placement tool for 3D FPGA integration is presented. The circuit is first divided into layers with limited number of inter-layer vias, and then placement is performed on individual layers, while minimizing the delay of critical paths. We use our tool as a platform for exploring potential benefits in terms of delay and wire-length that 3D technologies can offer for FPGA fabrics. We show that 3D integration results in wire-length reduction for FPGA designs. Our empirical analysis shows that wire-length can be reduced by up to 50% using ten layers. Delay reductions are estimated to be more than 30% if multi-segment lengths are employed between layers.

Keywords

Critical Path Delay Estimation Placement Algorithm Circuit Delay Wire Segment 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Reif, R., Fan, A., Chen, K.-N., Das, S.: Fabrication Technologies for Three-Dimensional Integrated Circuits. In: Proc. International Symposium on Quality Electronic Design, pp. 33–37 (2002)Google Scholar
  2. 2.
    Guarini, K.W., et al.: Electrical integrity of state-of-the-art 0.13um SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication. Technical Digest of the International Electron Devices Meeting, pp. 943–945 (2002)Google Scholar
  3. 3.
    Alexander, A.J., Cohoon, J.P., Colflesh, J.L., Karro, J., Peters, J.L., Robins, G.: Placement and Routing for Three-Dimensional FPGAs. In: Canadian Workshop on Field-Programmable Devices, pp. 11–18 (1996)Google Scholar
  4. 4.
    Alexander, A.J., Cohoon, J.P., Colflesh, J.L., Karro, J., Robins, G.: Three-Dimensional Field-Programmable Gate Arrays. In: Proc. International ASIC Conf., pp. 253–256 (1995)Google Scholar
  5. 5.
    Karro, J., Cohoon, J.P.: A spiffy tool for the simultaneous placement and global routing for three-dimensional field-programmable gate arrays. In: Great Lakes Symposium on VLSI, pp. 226–227 (1999)Google Scholar
  6. 6.
    Chiricescu, S., Leeser, M., Vai, M.M.: Design and Analysis of a Dynamically Reconfigurable Three-Dimensional FPGA. IEEE Trans. VLSI Systems 9(1), 186–196 (2001)CrossRefGoogle Scholar
  7. 7.
    Betz, V., Rose, J.: VPR: A New Packing Placement and Routing Tool for FPGA Research. Field-Programmable Logic App., 213-222 (1997)Google Scholar
  8. 8.
    Chiricescu, S.: Parametric Analysis of a Dynamically Reconfigurable Three-Dimensional FPGA. Ph.D. Dissertation, Northeastern University (1999)Google Scholar
  9. 9.
    Marquardt, A., Betz, V., Rose, J.: Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density. In: Proc. International FPGA Conf., pp. 37–46 (1999)Google Scholar
  10. 10.
    Karypis, G., Aggarwal, R., Kumar, V., Shekhar, S.: Multi-level Hypergraph Partitioning: Applications in VLSI Design. In: Proc. ACM/IEEE DAC, pp. 526–529 (1997)Google Scholar
  11. 11.
    Das, S., Chandrakasan, A., Reif, R.: Three-Dimensional Integrated Circuits: Performance Design Methodology and CAD Tools. In: Proc. International Symposium on VLSI, pp. 13–19 (2003)Google Scholar
  12. 12.
    Das, S., et al.: Technology, performance, and computer-aided design of three-dimensional integrated circuits. In: Proc. ACM/IEEE ISPD, pp. 108–115 (2004)Google Scholar
  13. 13.
    Rahman, A., Das, S., Chandrakasan, A., Reif, R.: Wiring Requirement and Three- Dimensional Integration of Field-Programmable Gate Arrays. In: Proc. ACM/IEEE SLIP, pp. 107–113 (2001)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Cristinel Ababei
    • 1
  • Pongstorn Maidee
    • 1
  • Kia Bazargan
    • 1
  1. 1.200 Union St. SE, ECE DepartmentUniversity of MinnesotaMinneapolisUSA

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