Exploring Potential Benefits of 3D FPGA Integration

  • Cristinel Ababei
  • Pongstorn Maidee
  • Kia Bazargan
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)


A new timing-driven partitioning-based placement tool for 3D FPGA integration is presented. The circuit is first divided into layers with limited number of inter-layer vias, and then placement is performed on individual layers, while minimizing the delay of critical paths. We use our tool as a platform for exploring potential benefits in terms of delay and wire-length that 3D technologies can offer for FPGA fabrics. We show that 3D integration results in wire-length reduction for FPGA designs. Our empirical analysis shows that wire-length can be reduced by up to 50% using ten layers. Delay reductions are estimated to be more than 30% if multi-segment lengths are employed between layers.


Critical Path Delay Estimation Placement Algorithm Circuit Delay Wire Segment 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Cristinel Ababei
    • 1
  • Pongstorn Maidee
    • 1
  • Kia Bazargan
    • 1
  1. 1.200 Union St. SE, ECE DepartmentUniversity of MinnesotaMinneapolisUSA

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