Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path

  • M. D. Galanis
  • G. Theodoridis
  • S. Tragoudas
  • D. Soudris
  • C. E. Goutis
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)


A high-performance reconfigurable coarse-grain data-path, part of a hybrid reconfigurable platform, is introduced. The data-path consists of coarse grain components that their flexibility and universality is shown to increase the system’s performance due to significant reductions in latency. An automated methodology for mapping applications on the proposed data-path is also presented. Results on DSP benchmarks show important performance improvements, up to 44%, over existing high-performance data-paths.


Clock Cycle Partial Match Register Bank Clock Period Data Flow Graph 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Hartenstein, R.: A Decade of Reconfigurable Computing: A Visionary Retrospective. In: Proc. of Design and Test in Europe (DATE), pp. 642–649 (2001)Google Scholar
  2. 2.
    Corazao, M.R., et al.: Performance Optimization Using Template Mapping for Datapath-Intensive High-Level Synthesis. IEEE Trans. on Computer Aided Design 15(2), 877–888 (1996)CrossRefGoogle Scholar
  3. 3.
    Kastner, R., et al.: Instruction Generation for Hybrid Reconfigurable Systems. ACM Trans. on Design Automation of Embedded Systems 7(4), 605–627 (2002)CrossRefGoogle Scholar
  4. 4.
    Cong, J., et al.: Application-Specific Instruction Generation for Configurable Processor Architectures. In: Proc. of the ACM Int. Symposium on FPGA, pp. 183–189 (2004)Google Scholar
  5. 5.
    De Micheli, G.: Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York (1994)Google Scholar
  6. 6.
    Leiserson, C.E.: Fat-Trees: Universal Networks for Hardware Efficient Supercomputing. IEEE Transactions on Computers 43(10), 892–901 (1985)Google Scholar
  7. 7.
    Synopsys Design Compiler© (2004),

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • M. D. Galanis
    • 1
  • G. Theodoridis
    • 2
  • S. Tragoudas
    • 3
  • D. Soudris
    • 4
  • C. E. Goutis
    • 1
  1. 1.University of Patras 
  2. 2.Aristotle University 
  3. 3.Southern Illinois UniversityUSA
  4. 4.Democritus UniversityGreece

Personalised recommendations